D-Link DIR-853 Rev A1

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DIR-853 Rev A1 is a dual-band (2.4G and 5G) router with 4 LAN ports and 1 WAN port. All ports can support 1Gbps. The hardware of this router is identical to DIR-853 Rev R1, but it has a different flash layout. Rev A1 and R1 use SPI Nor flash as the non-volatile storage, while Rev A3 uses NAND flash.

Front

Back

It is possible to install OpenWrt from the stock web interface without having to open the case of the router. Since 2018, D-Link added encryption to its firmware files and the stock web interface only accepts encrypted and valid firmware.

To walk around that and ease the installation of OpenWrt, first install this encrypted OpenWrt image (become dated), and then upgrade (using Luci Sysupgrade) to the latest OpenWrt:

https://github.com/openwrt/openwrt/files/10833430/dir-853-a1-fac-enc.bin.zip

The above image was generated by the imgcrypt encryption tool from an official OpenWrt factory image:

./imgcrypt openwrt-ramips-mt7621-dlink_dir-853-a1-squashfs-factory.bin dir-853-a1-fac-enc.bin

The imgcrypt tool is only available in source code at https://dlink-gpl.s3.amazonaws.com/GPL1700193/DIR853A2_V1.00B03.tar.gz.

You need to compile it on a 32-bit Linux or add 32-bit support to your AMD64 Linux distro.

See: https://forum.openwrt.org/t/re-dir-853-a2/152308/18

https://github.com/openwrt/openwrt/pull/12087

Basic configuration After flashing, proceed with this.

Known problems:

  • WLAN0 defaults to 5G after a fresh installation, to enable 2.4G network, you need to config it manually in LUCI.
  • If you see jffs2 related warnings/errors after updating from the stock web interface, you need to do a reset in LUCI. The error will be gone after a cold reboot.

generic.flashing.tftp

generic.debrick

Opening the case of the router may avoid its warranty. You may only consider this approach if you familiar with soldering. Otherwise, please proceed to OEM easy installation.

In this method, we first load an OpenWrt image into the RAM from the stock U-boot serial interface, then we install OpenWrt permanently to the flash.

  1. Open the case, and solder the 4-pin header near the WAN port.
  2. Connect it to a USB-UART TTL (3.3V) adapter, no need to connect VCC.
  3. Open a terminal emulator (e.g. screen /dev/ttyUSB0 on linux, or https://putty.org/ on Windows) with 57600 8N1.
  4. Setup a TFTP server on your PC that can serve xxx-ramips-mt7621-dlink_dir-853-a1-initramfs-kernel.bin.
  5. Connect any LAN port to your PC and set a static IPv4 address to 192.168.0.101 (netmask 255.255.255.0).
  6. Power on the device and keeps pressing 1 until you see the prompt.
  7. Use default IP addresses and enter the file name accordingly, then hit enter.
  8. Wait until it boots to OpenWrt, the default IP address is 192.168.1.1, you need to change your PC network adapter to use DHCP in order to access LUCI.
  9. So far, the OpenWrt runs in RAM and the flash contents are not touched. You can try OpenWrt without having to overwrite the stock firmware, a reboot clears all changes.
  10. Optionally, backup the stock firmware (the “firmware” partition) in Luci.
  11. To permantly install OpenWrt to the device , click on “System → Backup/Flash Firmware” in Luci and flash xxx-ramips-mt7621-dlink_dir-853-a1-squashfs-sysupgrade.bin

Note:

You should never flash images named xxx-initramfs-kernel.bin to the flash!

Stock (from Bootlog):

GD25Q128C(c8 40180000) (16384 Kbytes)
mtd .name = raspi, .size = 0x01000000 (16M) .erasesize = 0x00010000 (64K)
.numeraseregions = 0
Creating 7 MTD partitions on "raspi":
0x000000000000-0x000001000000 : "ALL"
0x000000000000-0x000000030000 : "Bootloader"
0x000000030000-0x000000040000 : "Config"
0x000000040000-0x000000050000 : "Factory"
0x000000050000-0x000000060000 : "Config2"
0x000000060000-0x000000fb0000 : "Kernel"
0x000000fb0000-0x000001000000 : "Private"

OpenWrt:

0x000000000000-0x000000030000 : "u-boot"
0x000000030000-0x000000040000 : "u-boot-env"
0x000000040000-0x000000050000 : "factory"
0x000000050000-0x000000060000 : "config2_stock"
0x000000060000-0x000000fb0000 : "firmware"
0x000000fb0000-0x000001000000 : "private_stock"
DIR-853 Rev A1 Flash Layout
Layer0 raw 16MB NOR SPI flash (GD25Q127CSIG, using GD25Q128C driver)
Layer1 mtd0 u-boot 192 KiB mtd1 u-boot-env 64 KiB mtd2 factory 64 KiB mtd3 config2_stock 64 KiB mtd4 firmware 15680 KiB mtd8 private_stock 320 KiB
Layer2 mtd5 kernel 2645 KiB mtd6 rootfs 13035 KiB
Layer3 mtd7 rootfs_data 8768 KiB
Mount Point none none none none none /rom as SquashFS, ro /overlay as JFFS2, rw none
/ as OverlayFS, rw

generic.sysupgrade

Both LuCI web upgrade and terminal upgrade works.

Interface Name Location on the flash Note
lan (eth2) @factory + 0xe000 on label
wan (eth3) @factory + 0xe006
2.4g (rax0) not on flash lan + 1
5g (ra0) not on flash lan + 2
  • LEDs: Power Blue+Orange,Wan Blue+Orange,WPS Blue,“2.4G”Blue, “5G” Blue, USB Blue
  • Buttons: Reset,WPS, Wifi

FIXME

  1. This table is automatically generated, once the correct filters for Brand and Model are set.
  2. If you see “Nothing.” instead of a table, please edit this section and adjust the filters with the proper Brand and Model. Just try, it's easy.
  3. If you still don't see a table here, or a table filled with '¿': Is there already a Techdata page available for D-Link DIR-853 A1? If not: Create one.
  4. If you see a table with the desired device data, everything is OK and you can delete this text and the <WRAP> that encloses it.
  5. If it still doesn't work: Don't panic, calm down, take a deep breath and contact a wiki admin (tmomas) for help.

---- datatemplatelist dttpllist ---- template: meta:template_datatemplatelist cols : Brand, Model, Versions, Device Type, Availability, Supported Since Commit_git, Supported since Rel, Supported current Rel, Unsupported, Bootloader, CPU, Target, CPU MHz, Flash MBs, RAM MB, Switch, Ethernet 100M ports_, Ethernet Gbit ports_, Comments network ports_, Modem, VLAN, WLAN 2.4GHz, WLAN 5.0GHz, WLAN Hardwares, WLAN Comments_, Detachable Antennas_, USB ports_, SATA ports_, Comments USB SATA ports_, Serial, JTAG, LED count, Button count, Power supply, Device Techdata_pageid, Forum topic URL_url, wikidevi URL_url, OEM Device Homepage URL_url, Firmware OEM Stock URL_url, Firmware OpenWrt Install URL_url, Firmware OpenWrt Upgrade URL_url, Comments_ filter : Brand=D-Link filter : Model=DIR-853 filter : Versions=A1


Remove four screws on the bottom of the device. No adhesive.

Note: This will void your warranty!

Main PCB:
filter: 0;
fileterIntensity: 0.0;
filterMask: 0;
algolist: 0;
multi-frame: 1;
brp_mask:8;
brp_del_th:0.0000,0.0000;
brp_del_sen:0.0500,0.0000;
module: photo; 
hw-remosaic: false; 
touch: (0.6554167, 0.38432294); 
sceneMode: 2621440; 
cct_value: 5631; 
AI_Scene: (-1, -1); 
aec_lux: 302.89227; 
aec_lux_index: 0; 
albedo: 0.0; 
confidence: 0.0; 
motionLevel: 0; 
weatherinfo: null; ...

port.serial general information about the serial port, serial port cable, etc.

The serial header locate near the power jack and it is not populated by default. Soldering is necessary.

Serial connection parameters
for D-Link DIR-853 A1
57600, 8N1, 3.3V

There is no need to connect Vcc to an external 3.3V.

Not verified!

There is an unpopulated USB 2.0 port on the PCB. To use it, you need to short circuit R31, LB15, R35, R38, and R37 on the PCB:

filter: 0;
fileterIntensity: 0.0;
filterMask: 0;
algolist: 0;
multi-frame: 1;
brp_mask:8;
brp_del_th:0.0012,0.0000;
brp_del_sen:1.0000,0.0000;
module: photo; 
hw-remosaic: false; 
touch: (0.5111806, 0.5566146); 
sceneMode: 3145728; 
cct_value: 5800; 
AI_Scene: (-1, -1); 
aec_lux: 359.4359; 
aec_lux_index: 0; 
albedo: 0.0; 
confidence: 0.0; 
motionLevel: 0; 
weatherinfo: null; ...

The pin out of the USB socket (from the top to bottom) is:

  1. Vcc, 5V
  2. D-
  3. D+
  4. GND

This port should work on the official OpenWrt firmware, as mt7621.dtsi suggests that it is enabled by default.

COPY HERE THE BOOTLOG WITH THE ORIGINAL FIRMWARE


=================================================================== MT7621 stage1 code 10:33:55 (ASIC) CPU=500000000 HZ BUS=166666666 HZ ================================================================== Change MPLL source from XTAL to CR... do MEMPLL setting.. MEMPLL Config : 0x11100000 3PLL mode + External loopback === XTAL-40Mhz === DDR-1200Mhz === PLL4 FB_DL: 0x6, 1/0 = 580/444 19000000 PLL2 FB_DL: 0x10, 1/0 = 563/461 41000000 PLL3 FB_DL: 0x11, 1/0 = 587/437 45000000 do DDR setting..[01F40000] Apply DDR3 Setting...(use customer AC) 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 -------------------------------------------------------------------------------- 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 000E:| 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 000F:| 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0010:| 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0011:| 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rank 0 coarse = 15 rank 0 fine = 72 B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 opt_dle value:9 DRAMC_R0DELDLY[018]=00001F20 ================================================================== RX DQS perbit delay software calibration ================================================================== 1.0-15 bit dq delay value ================================================================== bit| 0 1 2 3 4 5 6 7 8 9 -------------------------------------- 0 | 10 10 10 11 8 9 10 7 7 8 10 | 9 9 9 10 9 10 -------------------------------------- ================================================================== 2.dqs window x=pass dqs delay value (min~max)center y=0-7bit DQ of every group input delay:DQS0 =32 DQS1 = 31 ================================================================== bit DQS0 bit DQS1 0 (1~62)31 8 (1~58)29 1 (1~64)32 9 (1~60)30 2 (1~60)30 10 (1~62)31 3 (1~62)31 11 (0~57)28 4 (1~60)30 12 (1~60)30 5 (1~64)32 13 (1~60)30 6 (1~62)31 14 (1~62)31 7 (1~64)32 15 (1~61)31 ================================================================== 3.dq delay value last ================================================================== bit| 0 1 2 3 4 5 6 7 8 9 -------------------------------------- 0 | 11 10 12 12 10 9 11 7 9 9 10 | 9 12 10 11 9 10 ================================================================== ================================================================== TX perbyte calibration ================================================================== DQS loop = 15, cmp_err_1 = ffff0000 dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1 dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2 DQ loop=15, cmp_err_1 = ffff00a0 dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=1 DQ loop=14, cmp_err_1 = ffff0080 DQ loop=13, cmp_err_1 = ffff0000 dqs_perbyte_dly.last_dqdly_pass[0]=13, finish count=2 byte:0, (DQS,DQ)=(9,8) byte:1, (DQS,DQ)=(8,8) 20,data:89 [EMI] DRAMC calibration passed =================================================================== MT7621 stage1 code done CPU=500000000 HZ BUS=166666666 HZ =================================================================== U-Boot 1.1.3 (Jun 27 2019 - 20:25:37) Board: Ralink APSoC DRAM: 128 MB relocate_code Pointer at: 87fa8000 Config XHCI 40M PLL ****************************** Software System Reset Occurred ****************************** flash manufacture id: c8, device id 40 18 find flash: GD25Q128C ============================================ Ralink UBoot Version: 5.0.0.0 -------------------------------------------- ASIC MT7621A DualCore (MAC to MT7530 Mode) DRAM_CONF_FROM: Auto-Detection DRAM_TYPE: DDR3 DRAM bus: 16 bit Xtal Mode=3 OCP Ratio=1/3 Flash component: SPI Flash Date:Jun 27 2019 Time:20:25:37 ============================================ icache: sets:256, ways:4, linesz:32 ,total:32768 dcache: sets:256, ways:4, linesz:32 ,total:32768 ##### The CPU freq = 880 MHZ #### estimate memory size =128 Mbytes #Reset_MT7530 set LAN/WAN LLLLW ########RESET_GPIO_NUM: 8 Please choose the operation: 1: Load system code to SDRAM via TFTP. 2: Load system code then write to Flash via TFTP. 3: Boot system code via Flash (default). 4: Entr boot command line interface. 6: System Enter UBoot to Update Img or Bin. 7: Load Boot Loader code then write to Flash via Serial. 9: Load Boot Loader code then write to Flash via TFTP. default: 3 0 3: System Boot system code via Flash. ## Booting image at bc060000 ... Image Name: MIPS OpenWrt Linux-5.10.146 Image Type: MIPS Linux Kernel Image (lzma compressed) Data Size: 2708134 Bytes = 2.6 MB Load Address: 80001000 Entry Point: 80001000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK No initrd ## Transferring control to Linux (at address 80001000) ... ## Giving linux memsize in MB, 128 Starting kernel ... [ 0.000000] Linux version 5.10.146 (builder@buildhost) (mipsel-openwrt-linux-musl-gcc (OpenWrt GCC 11.2.0 r19803-9a599fee93) 11.2.0, GNU ld (GNU Binutils) 2.37) #0 SMP Fri Oct 14 22:44:41 2022 [ 0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3 [ 0.000000] printk: bootconsole [early0] enabled [ 0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc) [ 0.000000] MIPS: machine is D-Link DIR-853 A1 [ 0.000000] Initrd not found or empty - disabling initrd [ 0.000000] VPE topology {2,2} total 4 [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. [ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. [ 0.000000] Zone ranges: [ 0.000000] Normal [mem 0x0000000000000000-0x0000000007ffffff] [ 0.000000] HighMem empty [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000007ffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff] [ 0.000000] percpu: Embedded 15 pages/cpu s30256 r8192 d22992 u61440 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 32480 [ 0.000000] Kernel command line: console=ttyS0,57600 rootfstype=squashfs,jffs2 [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear) [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear) [ 0.000000] Writing ErrCtl register=00016080 [ 0.000000] Readback ErrCtl register=00016080 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.000000] Memory: 119472K/131072K available (7026K kernel code, 631K rwdata, 828K rodata, 1292K init, 243K bss, 11600K reserved, 0K cma-reserved, 0K highmem) [ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] rcu: Hierarchical RCU implementation. [ 0.000000] Tracing variant of Tasks RCU enabled. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. [ 0.000000] NR_IRQS: 256 [ 0.000000] CPU Clock: 880MHz [ 0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcaf478abb4, max_idle_ns: 440795247997 ns [ 0.000013] sched_clock: 64 bits at 880MHz, resolution 1ns, wraps every 4398046511103ns [ 0.015853] clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 4343773742 ns [ 0.033805] Calibrating delay loop... 586.13 BogoMIPS (lpj=2930688) [ 0.106122] pid_max: default: 32768 minimum: 301 [ 0.115430] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.129834] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.148078] rcu: Hierarchical SRCU implementation. [ 0.157881] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build [ 0.173444] smp: Bringing up secondary CPUs ... [ 0.183187] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. [ 0.183197] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.183209] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. [ 0.183284] CPU1 revision is: 0001992f (MIPS 1004Kc) [ 0.243287] Synchronize counters for CPU 1: done. [ 0.305407] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. [ 0.305417] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.305425] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. [ 0.305473] CPU2 revision is: 0001992f (MIPS 1004Kc) [ 0.364384] Synchronize counters for CPU 2: done. [ 0.424710] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. [ 0.424719] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.424728] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. [ 0.424781] CPU3 revision is: 0001992f (MIPS 1004Kc) [ 0.483959] Synchronize counters for CPU 3: done. [ 0.543570] smp: Brought up 1 node, 4 CPUs [ 0.555778] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns [ 0.575280] futex hash table entries: 1024 (order: 3, 32768 bytes, linear) [ 0.589099] pinctrl core: initialized pinctrl subsystem [ 0.601798] NET: Registered protocol family 16 [ 0.611696] thermal_sys: Registered thermal governor 'step_wise' [ 0.613145] cpuidle: using governor teo [ 0.671207] clocksource: Switched to clocksource GIC [ 0.682995] NET: Registered protocol family 2 [ 0.691984] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear) [ 0.707203] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear) [ 0.723831] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.739004] TCP bind hash table entries: 1024 (order: 1, 8192 bytes, linear) [ 0.752943] TCP: Hash tables configured (established 1024 bind 1024) [ 0.765714] UDP hash table entries: 256 (order: 1, 8192 bytes, linear) [ 0.778604] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear) [ 0.792725] NET: Registered protocol family 1 [ 0.801309] PCI: CLS 0 bytes, default 32 [ 0.811464] workingset: timestamp_bits=14 max_order=15 bucket_order=1 [ 0.828391] squashfs: version 4.0 (2009/01/31) Phillip Lougher [ 0.839898] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc. [ 0.860175] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251) [ 0.876552] mt7621_gpio 1e000600.gpio: registering 32 gpios [ 0.887905] mt7621_gpio 1e000600.gpio: registering 32 gpios [ 0.899236] mt7621_gpio 1e000600.gpio: registering 32 gpios [ 0.911221] Serial: 8250/16550 driver, 16 ports, IRQ sharing enabled [ 0.928100] printk: console [ttyS0] disabled [ 0.936579] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 19, base_baud = 3125000) is a 16550A [ 0.954502] printk: console [ttyS0] enabled [ 0.954502] printk: console [ttyS0] enabled [ 0.971027] printk: bootconsole [early0] disabled [ 0.971027] printk: bootconsole [early0] disabled [ 0.992973] spi-mt7621 1e000b00.spi: sys_freq: 220000000 [ 1.005150] spi-nor spi0.0: gd25q128 (16384 Kbytes) [ 1.014989] 6 fixed-partitions partitions found on MTD device spi0.0 [ 1.027693] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions [ 1.042271] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions [ 1.057656] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions [ 1.072275] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions [ 1.087061] Creating 6 MTD partitions on "spi0.0": [ 1.096617] 0x000000000000-0x000000030000 : "u-boot" [ 1.107509] 0x000000030000-0x000000040000 : "u-boot-env" [ 1.119251] 0x000000040000-0x000000050000 : "factory" [ 1.130404] 0x000000050000-0x000000060000 : "config2_stock" [ 1.142841] 0x000000060000-0x000000fb0000 : "firmware" [ 1.154222] 2 uimage-fw partitions found on MTD device firmware [ 1.166043] Creating 2 MTD partitions on "firmware": [ 1.175933] 0x000000000000-0x000000295346 : "kernel" [ 1.185842] mtd: partition "kernel" doesn't end on an erase/write block -- force read-only [ 1.203361] 0x000000295346-0x000000f50000 : "rootfs" [ 1.213272] mtd: partition "rootfs" doesn't start on an erase/write block boundary -- force read-only [ 1.232457] mtd: device 6 (rootfs) set to be root filesystem [ 1.243867] 1 squashfs-split partitions found on MTD device rootfs [ 1.256181] 0x0000006c0000-0x000000f50000 : "rootfs_data" [ 1.267905] 0x000000fb0000-0x000001000000 : "private_stock" [ 1.322403] mt7530 mdio-bus:1f: MT7530 adapts as multi-chip module [ 1.339352] mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 21 [ 1.357067] mtk_soc_eth 1e100000.ethernet wan: mediatek frame engine at 0xbe100000, irq 21 [ 1.374602] i2c /dev entries driver [ 1.384253] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges: [ 1.397659] mt7621-pci 1e140000.pcie: No bus range found for /pcie@1e140000, using [bus 00-ff] [ 1.415203] mt7621-pci 1e140000.pcie: MEM 0x0060000000..0x006fffffff -> 0x0000000000 [ 1.431507] mt7621-pci 1e140000.pcie: IO 0x001e160000..0x001e16ffff -> 0x0000000000 [ 1.447886] mt7621-pci 1e140000.pcie: Parsing DT failed [ 1.460516] NET: Registered protocol family 10 [ 1.471303] Segment Routing with IPv6 [ 1.478696] NET: Registered protocol family 17 [ 1.487665] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this. [ 1.513867] 8021q: 802.1Q VLAN Support v1.8 [ 1.525571] mt7530 mdio-bus:1f: MT7530 adapts as multi-chip module [ 1.554143] mt7530 mdio-bus:1f lan4 (uninitialized): PHY [mt7530-0:00] driver [MediaTek MT7530 PHY] (irq=26) [ 1.576200] mt7530 mdio-bus:1f lan3 (uninitialized): PHY [mt7530-0:01] driver [MediaTek MT7530 PHY] (irq=27) [ 1.598237] mt7530 mdio-bus:1f lan2 (uninitialized): PHY [mt7530-0:02] driver [MediaTek MT7530 PHY] (irq=28) [ 1.620329] mt7530 mdio-bus:1f lan1 (uninitialized): PHY [mt7530-0:03] driver [MediaTek MT7530 PHY] (irq=29) [ 1.643277] mt7530 mdio-bus:1f: configuring for fixed/rgmii link mode [ 1.660099] DSA: tree 0 setup [ 1.666369] rt2880-pinmux pinctrl: pcie is already enabled [ 1.677406] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges: [ 1.690785] mt7621-pci 1e140000.pcie: No bus range found for /pcie@1e140000, using [bus 00-ff] [ 1.708310] mt7621-pci 1e140000.pcie: MEM 0x0060000000..0x006fffffff -> 0x0000000000 [ 1.724609] mt7621-pci 1e140000.pcie: IO 0x001e160000..0x001e16ffff -> 0x0000000000 [ 1.741005] mt7621-pci-phy 1e149000.pcie-phy: PHY for 0xbe149000 (dual port = 1) [ 1.756080] mt7621-pci-phy 1e14a000.pcie-phy: PHY for 0xbe14a000 (dual port = 0) [ 1.771056] mt7621-pci 1e140000.pcie: failed to parse bus ranges property: -22 [ 1.885676] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz [ 1.896793] mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz [ 2.008087] mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK) [ 2.021953] mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK) [ 2.035828] mt7621-pci 1e140000.pcie: PCIE0 enabled [ 2.045545] mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002 [ 2.064237] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00 [ 2.076912] pci_bus 0000:00: root bus resource [io 0x1e160000-0x1e16ffff] [ 2.090605] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] [ 2.104311] pci_bus 0000:00: root bus resource [bus 00-ff] [ 2.115243] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff]) [ 2.135558] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400 [ 2.147535] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x7fffffff] [ 2.160029] pci 0000:00:00.0: reg 0x14: [mem 0x60200000-0x6020ffff] [ 2.172588] pci 0000:00:00.0: supports D1 [ 2.180556] pci 0000:00:00.0: PME# supported from D0 D1 D3hot [ 2.193637] pci 0000:01:00.0: [14c3:7615] type 00 class 0x000280 [ 2.205659] pci 0000:01:00.0: reg 0x10: initial BAR value 0x00000000 invalid [ 2.219704] pci 0000:01:00.0: reg 0x10: [mem size 0x00100000 64bit] [ 2.232378] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5.0 GT/s PCIe x1 link) [ 2.263333] pci 0000:00:00.0: PCI bridge to [bus 01-ff] [ 2.273774] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff] [ 2.285909] pci 0000:00:00.0: bridge window [mem 0x60000000-0x600fffff] [ 2.299438] pci 0000:00:00.0: bridge window [mem 0x60100000-0x601fffff pref] [ 2.313832] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 [ 2.327044] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000] [ 2.340217] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000] [ 2.354100] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff] [ 2.367620] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref] [ 2.382010] pci 0000:00:00.0: BAR 1: assigned [mem 0x60200000-0x6020ffff] [ 2.395544] pci 0000:00:00.0: BAR 7: assigned [io 0x1e160000-0x1e160fff] [ 2.409069] pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x600fffff 64bit] [ 2.423645] pci 0000:00:00.0: PCI bridge to [bus 01] [ 2.433537] pci 0000:00:00.0: bridge window [io 0x1e160000-0x1e160fff] [ 2.447053] pci 0000:00:00.0: bridge window [mem 0x60000000-0x600fffff] [ 2.460572] pci 0000:00:00.0: bridge window [mem 0x60100000-0x601fffff pref] [ 2.483113] VFS: Mounted root (squashfs filesystem) readonly on device 31:6. [ 2.501585] Freeing unused kernel memory: 1292K [ 2.510618] This architecture does not have kernel memory protection. [ 2.523474] Run /sbin/init as init process [ 2.532065] mt7530 mdio-bus:1f: Link is Up - 1Gbps/Full - flow control rx/tx [ 3.091762] init: Console is alive [ 3.098900] init: - watchdog - [ 3.926495] kmodloader: loading kernel modules from /etc/modules-boot.d/* [ 4.057736] usbcore: registered new interface driver usbfs [ 4.068905] usbcore: registered new interface driver hub [ 4.079652] usbcore: registered new device driver usb [ 4.094916] uhci_hcd: USB Universal Host Controller Interface driver [ 4.115431] xhci-mtk 1e1c0000.xhci: supply vbus not found, using dummy regulator [ 4.130503] xhci-mtk 1e1c0000.xhci: supply vusb33 not found, using dummy regulator [ 4.145861] xhci-mtk 1e1c0000.xhci: xHCI Host Controller [ 4.156504] xhci-mtk 1e1c0000.xhci: new USB bus registered, assigned bus number 1 [ 4.181382] xhci-mtk 1e1c0000.xhci: hcc params 0x01401198 hci version 0x96 quirks 0x0000000000290010 [ 4.199680] xhci-mtk 1e1c0000.xhci: irq 20, io mem 0x1e1c0000 [ 4.212492] hub 1-0:1.0: USB hub found [ 4.220110] hub 1-0:1.0: 2 ports detected [ 4.228828] xhci-mtk 1e1c0000.xhci: xHCI Host Controller [ 4.239493] xhci-mtk 1e1c0000.xhci: new USB bus registered, assigned bus number 2 [ 4.254455] xhci-mtk 1e1c0000.xhci: Host supports USB 3.0 SuperSpeed [ 4.267337] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. [ 4.284367] hub 2-0:1.0: USB hub found [ 4.292128] hub 2-0:1.0: 1 port detected [ 4.307798] kmodloader: done loading kernel modules from /etc/modules-boot.d/* [ 4.341696] init: - preinit - [ 5.141616] random: jshn: uninitialized urandom read (4 bytes read) [ 5.225812] random: jshn: uninitialized urandom read (4 bytes read) [ 5.276679] random: jshn: uninitialized urandom read (4 bytes read) [ 5.558866] mtk_soc_eth 1e100000.ethernet eth0: configuring for fixed/rgmii link mode [ 5.575074] mtk_soc_eth 1e100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx [ 5.581722] mt7530 mdio-bus:1f lan1: configuring for phy/gmii link mode [ 5.605420] 8021q: adding VLAN 0 to HW filter on device lan1 [ 5.619351] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready Press the [f] key and hit [enter] to enter failsafe mode Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level [ 9.844537] jffs2: notice: (594) jffs2_build_xattr_subsystem: complete building xattr subsystem, 17 of xdatum (7 unchecked, 6 orphan) and 33 of xref (16 dead, 3 orphan) found. [ 9.877692] mount_root: switching to jffs2 overlay [ 9.890793] overlayfs: upper fs does not support tmpfile. [ 9.913579] urandom-seed: Seeding with /etc/urandom.seed [ 10.035393] procd: - early - [ 10.041547] procd: - watchdog - [ 10.691412] procd: - watchdog - [ 10.800394] procd: - ubus - [ 10.939918] random: ubusd: uninitialized urandom read (4 bytes read) [ 10.962090] random: ubusd: uninitialized urandom read (4 bytes read) [ 10.975230] random: ubusd: uninitialized urandom read (4 bytes read) [ 10.993925] procd: - init - Please press Enter to activate this console. [ 11.302010] random: crng init done [ 11.308805] random: 23 urandom warning(s) missed due to ratelimiting [ 11.805305] kmodloader: loading kernel modules from /etc/modules.d/* [ 11.959625] urngd: v1.0.2 started. [ 12.114454] Loading modules backported from Linux version v5.15.58-0-g7d8048d4e064 [ 12.129581] Backport generated by backports.git v5.15.58-1-0-g42a95ce7 [ 12.357815] mt7621-pci 1e140000.pcie: bus=1 slot=0 irq=22 [ 12.368632] pci 0000:00:00.0: enabling device (0006 -> 0007) [ 12.379910] mt7615e 0000:01:00.0: enabling device (0000 -> 0002) [ 12.422109] mt7615e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20180518100604a [ 12.422109] [ 12.463889] PPP generic driver version 2.4.2 [ 12.474259] NET: Registered protocol family 24 [ 12.491054] kmodloader: done loading kernel modules from /etc/modules.d/* [ 12.779876] mt7615e 0000:01:00.0: N9 Firmware Version: _reserved_, Build Time: 20200814163649 [ 12.893605] mt7615e 0000:01:00.0: CR4 Firmware Version: _reserved_, Build Time: 20190121161307 [ 21.120643] mtk_soc_eth 1e100000.ethernet eth0: Link is Down [ 21.142190] mtk_soc_eth 1e100000.ethernet eth0: configuring for fixed/rgmii link mode [ 21.158173] mtk_soc_eth 1e100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx [ 21.161890] mt7530 mdio-bus:1f lan1: configuring for phy/gmii link mode [ 21.188685] 8021q: adding VLAN 0 to HW filter on device lan1 [ 21.202988] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready [ 21.216612] br-lan: port 1(lan1) entered blocking state [ 21.227152] br-lan: port 1(lan1) entered disabled state [ 21.238594] device lan1 entered promiscuous mode [ 21.248127] device eth0 entered promiscuous mode [ 21.281800] mt7530 mdio-bus:1f lan2: configuring for phy/gmii link mode [ 21.295744] 8021q: adding VLAN 0 to HW filter on device lan2 [ 21.310521] br-lan: port 2(lan2) entered blocking state [ 21.321272] br-lan: port 2(lan2) entered disabled state [ 21.333088] device lan2 entered promiscuous mode [ 21.356209] mt7530 mdio-bus:1f lan3: configuring for phy/gmii link mode [ 21.370017] 8021q: adding VLAN 0 to HW filter on device lan3 [ 21.385072] br-lan: port 3(lan3) entered blocking state [ 21.395668] br-lan: port 3(lan3) entered disabled state [ 21.407601] device lan3 entered promiscuous mode [ 21.429562] mt7530 mdio-bus:1f lan4: configuring for phy/gmii link mode [ 21.443399] 8021q: adding VLAN 0 to HW filter on device lan4 [ 21.458194] br-lan: port 4(lan4) entered blocking state [ 21.468678] br-lan: port 4(lan4) entered disabled state [ 21.480536] device lan4 entered promiscuous mode [ 21.508096] mtk_soc_eth 1e100000.ethernet wan: PHY [mdio-bus:04] driver [MediaTek MT7530 PHY] (irq=POLL) [ 21.527082] mtk_soc_eth 1e100000.ethernet wan: configuring for phy/rgmii-rxid link mode


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  • Last modified: 2024/02/13 05:08
  • by rikka0w0