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toh:aztech:gr7000

Aztech GR7000

Hardware Highlights

CPU Ram Flash Network USB Serial JTag
Lantiq XWAY ARX168 AR9 @ 333MHz 32MiB 8MiB 5 x 1 Yes Yes Yes

Info

Architecture MIPS32
Vendor soc.lantiq Lantiq
bootloader U-Boot 1.1.5-LANTIQ-v-1.8.20
System-On-Chip Infineon/Lantiq XWAY ARX168
CPU/Speed MIPS 34Kc / 333MHz
Flash-Chip Spansion S29GL064N90TF104
Flash size 8MB
RAM 32MB HYNIX H5DU2562GTR-E3C
Wireless Ralink RT3062F 802.11bgn
Ethernet Atheros AR8316 5 x Gigabit
USB Yes 2 x 2.0 (driver dwc_otg)
Serial Yes
JTAG Yes

Original Flash Layout

flash.layout for explanations!

dev: size erasesize name
mtd0: 00010000 00002000 “u-boot”
mtd1: 007f0000 00010000 “rootfs”

Serial

Pinout

Now connect a serial hack adapter (DKU-5, CA-42 or similar containing the PL-2303 chip) and away you go!
The right settings for accessing the serial console are as follows:

Bits per second: 115200
Data bits: 8
Stop bits: 1
Parity: None
Flow control: None

JTAG

port.jtag general information about the JTAG port, JTAG cable, etc.

How to connect to the JTAG Port of this specific device:
Insert photo of PCB with markings for JTAG port

CPU Info

system type             : AR9
processor               : 0
cpu model               : MIPS 34K V4.12
BogoMIPS                : 222.00
wait instruction        : yes
microsecond timers      : yes
tlb_entries             : 16
extra interrupt vector  : yes
hardware watchpoint     : yes
ASEs implemented        : mips16 dsp mt
VCED exceptions         : not available
VCEI exceptions         : not available

Flash Layout Log

Environment size: 3343/4092 bytes
AMAZON_S # run update_firmware
Using amazon_s Switch device
TFTP from server 192.168.1.2; our IP address is 192.168.1.1
Filename 'firmware.img'.
Load address: 0x80800000
Loading: #################################################################
         #################################################################
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         ################################################################
done
Bytes transferred = 5316488 (511f88 hex)
Image contains header with name [IFXCPE RootFS]
Un-Protected 64 sectors

 done

........................ done
Partial erased from 0xb0010000 to 0xb0406a6f
Protected 64 sectors
Protect off B07FE000 ... B07FEFFF
Un-Protected 1 sectors
Erasing Flash...
 done
Partial erased from 0xb07fe000 to 0xb07fefff
Writing to Flash... done
Protected 1 sectors
Image contains header with name [MIPS IFXCPE Linux-2.6.20.19]
Un-Protected 18 sectors

 done

 done

...... done
Partial erased from 0xb06d2b70 to 0xb07edfff
Protected 18 sectors
Protect off B07FE000 ... B07FEFFF
Un-Protected 1 sectors
Erasing Flash...
 done
Partial erased from 0xb07fe000 to 0xb07fefff
Writing to Flash... done
Protected 1 sectors

System Info

# cat /proc/kmsg <5>Linux version 2.6.20.19 <4> (ramesh@rdfwsrv.aztech.com) (gcc version 3.4.6 (OpenWrt-2.0)) #1 Fri Aug 26 17:51:59 SGT 2011 <4>phym = 02000000, mem = 01f00000, max_pfn = 00001f00 <4>Reserving memory for CP1 @0xa1f00000, size 0x00100000 <4>CPU revision is: 0001954c <4>Determined physical RAM map: <4>User-defined physical RAM map: <4> memory: 01f00000 @ 00000000 (usable) <6>Initrd not found or empty - disabling initrd <7>On node 0 totalpages: 7936 <7> DMA zone: 62 pages used for memmap <7> DMA zone: 0 pages reserved <7> DMA zone: 7874 pages, LIFO batch:0 <7> Normal zone: 0 pages used for memmap <4>Built 1 zonelists. Total pages: 7874 <5>Kernel command line: root=/dev/mtdblock1 ro rootfstype=squashfs ip=192.168.1.1:192.168.1.2::::eth0:on console=ttyS1,115200 ethaddr=00:26:75:36:A8:22 phym=32M mem=31M panic=1 mtdparts=ifx_nor0:64k(uboot),-(rootfs) init=/etc/preinit quiet vpe1_load_addr=0x81f00000 vpe1_mem=1M ethwan=2 <6>1 MIPSR2 register sets available <4>Primary instruction cache 32kB, physically tagged, 4-way, linesize 32 bytes. <4>Primary data cache 16kB, 4-way, linesize 32 bytes. <6>Synthesized TLB refill handler (20 instructions). <6>Synthesized TLB load handler fastpath (32 instructions). <6>Synthesized TLB store handler fastpath (32 instructions). <6>Synthesized TLB modify handler fastpath (31 instructions). <6>Cache parity protection disabled <6>Lantiq ICU driver, version 3.0.1, (c) 2001-2010 Lantiq Deutschland GmbH <4>PID hash table entries: 128 (order: 7, 512 bytes) <4>Using 166.667 MHz high precision timer. <4>Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) <4>Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) <6>Memory: 27620k/31744k available (2743k kernel code, 4124k reserved, 655k data, 180k init, 0k highmem) <7>Calibrating delay loop... 222.00 BogoMIPS (lpj=1110016) <6>Security Framework v1.0.0 initialized <4>Mount-cache hash table entries: 512 <6>NET: Registered protocol family 16 <6>Lantiq PCI host controller driver, version 1.1.5, (c) 2001-2010 Lantiq Deutschland GmbH <5>SCSI subsystem initialized <6>usbcore: registered new interface driver usbfs <6>usbcore: registered new interface driver hub <6>usbcore: registered new device driver usb <6>NET: Registered protocol family 2 <4>IP route cache hash table entries: 1024 (order: 0, 4096 bytes) <4>TCP established hash table entries: 1024 (order: 0, 4096 bytes) <4>TCP bind hash table entries: 512 (order: -1, 2048 bytes) <6>TCP: Hash tables configured (established 1024 bind 512) <6>TCP reno registered <6>gptu: totally 6 16-bit timers/counters <6>gptu: misc_register on minor 63 <6>gptu: succeeded to request irq 118 <6>gptu: succeeded to request irq 119 <6>gptu: succeeded to request irq 120 <6>gptu: succeeded to request irq 121 <6>gptu: succeeded to request irq 122 <6>gptu: succeeded to request irq 123 <6>IFX DMA driver, version ifxmips_dma_core.c:v1.0.8 <4>,(c)2009 Infineon Technologies AG <6>Lantiq CGU driver, version 1.0.9, (c) 2001-2010 Lantiq Deutschland GmbH <4>Wired TLB entries for Linux read_c0_wired() = 0 <6>squashfs: version 3.2-r2 (2007/01/15) Phillip Lougher <4>squashfs: LZMA suppport for slax.org by jro <6>Infineon Technologies DEU driver version 1.0.1 <5>IFX DEU DES initialized (multiblock). <5>IFX DEU AES initialized (multiblock). <5>IFX DEU ARC4 initialized (multiblock). <5>IFX DEU SHA1 initialized. <5>IFX DEU MD5 initialized. <5>IFX DEU SHA1_HMAC initialized. <5>IFX DEU MD5_HMAC initialized. <6>io scheduler noop registered (default) <6>HDLC line discipline: version $Revision: 4.8 $, maxframe=4096 <6>N_HDLC line discipline registered. <4>PMCU initiates! <6>ifx_pmu_init: Major 253 <6>Lantiq PMU driver, version 1.0.6, (c) 2001-2010 Lantiq Deutschland GmbH <6>Lantiq GPIO driver, version 1.2.12, (c) 2001-2010 Lantiq Deutschland GmbH <3>drivers/char/ifxmips_rcu.c:668:ifx_rcu_init: Can not register RCU device - -16 <6>Lantiq LED Controller driver, version 1.0.4, (c) 2001-2010 Lantiq Deutschland GmbH <4>IFX MEI Version 5.00.04<6>Aztech Button driver has been initialized <6>ttyS0 at MMIO 0xbe100400 (irq = 98) is a IFX_ASC <6>ttyS1 at MMIO 0xbe100c00 (irq = 105) is a IFX_ASC <6>Lantiq ASC (UART) driver, version 1.0.5, (c) 2001-2010 Lantiq Deutschland GmbH <4>RAMDISK driver initialized: 1 RAM disks of 12288K size 1024 blocksize <6>loop: loaded (max 8 devices) <6>PPP generic driver version 2.4.2 <6>PPP Deflate Compression module registered <6>PPP BSD Compression module registered <6>PPP MPPE Compression module registered <6>NET: Registered protocol family 24 <4>IFX SWITCH API, Version 0.8.7.6.3 <6>SWAPI: Registered character device [switch_api] with major no [81] <4>Loading D5 (MII0/1) driver ...... Succeeded! <4>PPE datapath driver info: <4> Version ID: 192.3.3.1.0.0.3 <4> Family : GR9 <4> DR Type : Normal Data Path | Indirect-Fast Path <4> Interface : MII0 | MII1 <4> Mode : Routing <4> Release : 0.0.3 <4>PPE firmware info: <4> Version ID: 6.2.1.6.1.10 <4> Family : GR9 <4> FW Type : Acceleration <4> Interface : MII0 + MII1 <4> Mode : Bridging + IPv4 Routing <4> Release : 1.10 <4>PPA API --- init successfully <6>ifx_nor0: Found 1 x16 devices at 0x0 in 16-bit bank <4> Amd/Fujitsu Extended Query Table at 0x0040 <5>number of CFI chips: 1 <5>cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness. <5>2 cmdlinepart partitions found on MTD device ifx_nor0 <6>ifx_mtd_init flash0: Using dynamic image partition <5>Creating 2 MTD partitions on "ifx_nor0": <5>0x00000000-0x00010000 : "uboot" <5>0x00010000-0x00800000 : "rootfs" <6>Lantiq MTD NOR driver, version 1.0.4, (c) 2001-2010 Lantiq Deutschland GmbH <6>Lantiq SSC driver, version 2.1.5, (c) 2001-2010 Lantiq Deutschland GmbH <4>Unknown SPI device: 0xFF 0xFF 0xFF <4>ifx_spi_flash_init: Found no serial flash device <5>usbmon: debugfs is not available <6>usbcore: registered new interface driver usblp <6>drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver <6>Initializing USB Mass Storage driver... <6>usbcore: registered new interface driver usb-storage <6>USB Mass Storage support registered. <6>pegasus: v0.6.14 (2006/09/27), Pegasus/Pegasus II USB Ethernet driver <6>usbcore: registered new interface driver pegasus <6>Registered led device: ledc_0 <6>Registered led device: broadband_led <6>Registered led device: internet_led <6>Registered led device: internet_red_led <6>Registered led device: power_led <6>Registered led device: ledc_5 <6>Registered led device: ledc_6 <6>Registered led device: usbdev_led <6>Registered led device: ledc_8 <6>Registered led device: ledc_9 <6>Registered led device: ledc_10 <6>Registered led device: pstn_led <6>Registered led device: voip2_led <6>Registered led device: voip_led <6>Registered led device: ledc_14 <6>Registered led device: wps_led <6>Lantiq LED driver, version 1.0.14, (c) 2001-2010 Lantiq Deutschland GmbH <4>nf_conntrack version 0.5.0 (248 buckets, 1984 max) <4>nf_ct_ftp: registering helper for pf: 2 port: 21 <4>nf_ct_ftp: registering helper for pf: 10 port: 21 <4>ip_conntrack_rtsp v0.6.21 loading <6>GRE over IPv4 tunneling driver <4>ip_nat_rtsp v0.6.21 loading <4>ip_tables: (C) 2000-2006 Netfilter Core Team <4>ipt_time loading <6>TCP cubic registered <6>NET: Registered protocol family 1 <6>NET: Registered protocol family 17 <6>802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> <6>All bugs added by David S. Miller <davem@redhat.com> <6>ieee80211: 802.11 data/management/control stack, git-1.1.13 <6>ieee80211: Copyright (C) 2004-2005 Intel Corporation <jketreno@linux.intel.com> <7>ieee80211_crypt: registered algorithm 'NULL' <7>ieee80211_crypt: registered algorithm 'WEP' <7>ieee80211_crypt: registered algorithm 'CCMP' <7>ieee80211_crypt: registered algorithm 'TKIP' <4>VFS: Mounted root (squashfs filesystem) readonly. <6>Freeing unused kernel memory: 180k freed <6>Time: MIPS clocksource has been installed. <4>Warning: unable to open an initial console. <4>Algorithmics/MIPS FPU Emulator v1.5 <4>echo <enable/disable> [sw/mii0/mii1] > /proc/eth/flowcontrol <4>echo <enable/disable> [sw/mii0/mii1] > /proc/eth/flowcontrol <4>echo <enable/disable> [sw/mii0/mii1] > /proc/eth/flowcontrol <4>fuse init (API version 7.8) <4>fuse distribution version: 2.7.3 <6>IFXOS, Version 1.5.11 <6>(c) Copyright 2007, Infineon Technologies AG <6>### IFXOS - IFXOS - IFXOS - IFXOS ### ifx_ppa_init - init succeeded <4>ifx_nfext_core: module license 'NON-GPL' taints kernel. <7>PCI: Setting latency timer of device 0000:00:0e.0 to 64 <4> <4> <4>=== pAd = c0021000, size = 514400 === <4> <4><-- RTMPAllocAdapterBlock, Status=0 <4>pAd->CSRBaseAddress =0xb8000000, csr_addr=0xb8000000! <4>/home/ramesh/GR7K/UGW-4.2/build_dir/linux-ifxcpe_grx_gw_he_ethwan/rt3062-2.5.0.2/Module/os/linux/../../os/linux/rt_linux.c:214 assert memfailed <4>RtmpOSNetDevDetach(): RtmpOSNetDeviceDetach(), dev->name=ra0! <4> <4> <4>=== pAd = c0021000, size = 514400 === <4> <4><-- RTMPAllocAdapterBlock, Status=0 <4>pAd->CSRBaseAddress =0xb8000000, csr_addr=0xb8000000! <6>device eth0 entered promiscuous mode <4>RX DESC a15b1000 size = 2048 <4><-- RTMPAllocTxRxRingMemory, Status=0 <4>1. Phy Mode = 9 <4>2. Phy Mode = 9 <4>NVM is Efuse and its size =3c[3c0-3fb] <4>3. Phy Mode = 9 <4>MCS Set = ff ff 00 00 01 <4>Main bssid = 00:26:75:36:a8:24 <4><==== rt28xx_init, Status=0 <4>0x1300 = 000a4380 <6>device ra0 entered promiscuous mode <6>br0: port 2(ra0) entering learning state <6>br0: port 1(eth0) entering learning state <6>br0: topology change detected, propagating <6>br0: port 2(ra0) entering forwarding state <6>br0: topology change detected, propagating <6>br0: port 1(eth0) entering forwarding state # cat /proc/locks 1: FLOCK ADVISORY WRITE 2394 00:09:2984 0 EOF # cat /proc/mips/mtsched VPE[0].VPEschedule = 0x00000020 VPE[0].VPEschefback = 0xffffffff VPE[1].VPEschedule = 0x00000000 VPE[1].VPEschefback = 0x00000000 TC[0].TCschedule = 0x00000000 TC[0].TCschefback = 0xffffffff TC[1].TCschedule = 0x00000000 TC[1].TCschefback = 0x203f44d3 # cat /proc/ppa/api/ver PPA Sub System info: Version ID: 2.3.7 PPA API driver info: Version ID: 96.32.7.3.0.0.4 Family : AR9 | GR9 DR Type : PPA API Interface : MII0 | MII1 | ATM Mode : Routing | Bridging Release : 0.0.4 PPA Stack Adaption Layer driver info: Version ID: 96.16.0.0.0.0.3 Family : AR9 | GR9 DR Type : OS Adatpion Layer Interface : N/A Mode : N/A Release : 0.0.3 PPE HAL driver info: Version ID: 192.4.3.1.0.0.2 Family : GR9 DR Type : HAL Interface : MII0 | MII1 Mode : Routing Release : 0.0.2 PPE firmware info: Version ID: 6.2.1.6.1.10 Family : GR9 FW Type : Acceleration Interface : MII0 + MII1 Mode : Bridging + IPv4 Routing Release : 1.10 # # cat /proc/ppa/hal/d5/ /proc/ppa/hal/d5/genconf /proc/ppa/hal/d5/mtu /proc/ppa/hal/d5/hit /proc/ppa/hal/d5/out_vlan /proc/ppa/hal/d5/ipv6_ip /proc/ppa/hal/d5/pppoe /proc/ppa/hal/d5/mac /proc/ppa/hal/d5/route /proc/ppa/hal/d5/mc /proc/ppa/hal/d5/ver /proc/ppa/hal/d5/mib # cat /proc/ppa/hal/d5/genconf ETH_PORTS_CFG (0xBE1A0090): WAN VLAN ID Hi - 4095, WAN VLAN ID Lo - 3 LAN_ROUT_TBL_CFG (0xBE1A0098): num - 64, TTL check - on, no hit drop - off IP checksum - off, TCP/UDP checksum - off, checksum error drop - off WAN_ROUT_TBL_CFG (0xBE1A009C): num - 64, TTL check - on, no hit drop - off MC num - 64, MC drop - off IP checksum - off, TCP/UDP checksum - off, checksum error drop - off GEN_MODE_CFG1 (0xBE1A00A0): App2 - indirect, U/S - direct, U/S early discard - disable classification table entry - 32, IPv6 route entry - 2 session based rate control - disable, IPv4 WAN ingress hash alg - dest port multiple field based classification and VLAN assignment for bridging - disable D/S IPv4 multicast acceleration - IP/port pairs, IPv6 acceleration - enable WAN acceleration - enable, LAN acceleration - enable, switch isolation - isolated WAN Interfaces: ETH1 LAN Interfaces: ETH0 EXT1 EXT2 EXT3 EXT4 EXT5 GEN_MODE_CFG2 (0xBE1A00A4): 0 - off 1 - off 2 - off 3 - off 4 - off 5 - off 6 - off 7 - off TX_QOS_CFG (0xBE1A0048): time_tick - 0, overhd_bytes - 0, eth1_eg_qnum - 0 eth1_burst_chk - off, eth1 - HW QoS, rate shaping - off, WFQ - off KEY_SEL_n (0xBE1A00B0): 00000000 00000000 4e4f8081 52430000 # cat /proc/misc 229 fuse 63 gptu # cat /proc/modules ifxusb_host 101216 0 - Live 0xc00d4000 rt3562ap 1070448 1 - Live 0xc0177000 (P) ifx_nfext_ppp 1200 0 - Live 0xc0006000 (P) ifx_nfext_core 1776 1 ifx_nfext_ppp, Live 0xc0004000 (P) drv_ifxos 18624 0 - Live 0xc000a000 fuse 46960 0 - Live 0xc0014000 # cat /proc/iomem 00000000-01efffff : System RAM 00002144-002afd9b : Kernel code 002afd9c-00353d7f : Kernel data 18000000-1a000000 : PCI Memory resources 18000000-1800ffff : 0000:00:0e.0 18000000-1800ffff : 0000:00:0e.0 1e101000-1e101fff : ifxusb_hcd 1e106000-1e106fff : ifxusb_hcd 1e120000-1e12ffff : ifxusb_hcd 1e140000-1e15ffff : ifxusb_hcd 1e1c0000-1e1dffff : ifxusb_hcd 1e1e0000-1e1effff : ifxusb_hcd # cat /proc/ioports 1ae00000-1b000000 : PCI I/O resources # cat /proc/interrupts CPU0 15: 5 IFX_ICU ifx_ssc_tx 22: 25961 IFX_ICU ra0 34: 0 EIC mii1_gphy_isr 53: 0 IFX_ICU DYING_GASP 54: 0 IFX_ICU ifxusb_hcd_1:usb1 55: 0 IFX_ICU DFEIR 62: 0 IFX_ICU dma-core 64: 2 IFX_ICU dma-core 65: 0 IFX_ICU dma-core 67: 0 IFX_ICU dma-core 69: 0 IFX_ICU dma-core 70: 992 IFX_ICU dma-core 71: 0 IFX_ICU dma-core 72: 0 IFX_ICU dma-core 73: 0 IFX_ICU dma-core 74: 0 IFX_ICU dma-core 75: 0 IFX_ICU dma-core 80: 0 IFX_ICU dma-core 83: 0 IFX_ICU ifxusb_hcd_2:usb2 85: 0 IFX_ICU dma-core 88: 0 IFX_ICU d5_mailbox_isr 89: 0 IFX_ICU dma-core 90: 0 IFX_ICU dma-core 91: 0 IFX_ICU dma-core 92: 0 IFX_ICU dma-core 93: 0 IFX_ICU dma-core 103: 845 IFX_ICU asc1_tx 105: 0 IFX_ICU asc1_rx 106: 0 IFX_ICU asc1_err 118: 0 IFX_ICU gptu 119: 0 IFX_ICU gptu 120: 0 IFX_ICU gptu 121: 0 IFX_ICU gptu 122: 0 IFX_ICU gptu 123: 0 IFX_ICU gptu 159: 0 IFX_ICU perf_ctr 176: 56534 TIMER timer ERR: 0 # cat /proc/driver/ifx_dma/ifx_dma_register General DMA Registers ----------------------------------------- CLC= 00000000 ID= 01454c06 DMA_CPOLL= 80000040 DMA_CS= 00000005 DMA_PS= 00000002 DMA_IRNEN= 000030ff DMA_IRNCR= 00000000 DMA_IRNICR= 00000000 DMA Channel Registers ----------------------------------------- Channel 0 - Device PPE Rx DMA_CCTRL= 00010001 DMA_CDBA= 010f0000 DMA_CIE= 0000000a DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 1 - Device PPE Tx DMA_CCTRL= 01010101 DMA_CDBA= 1e1a6c00 DMA_CIE= 00000000 DMA_CIS= 00000004 DMA_CDLEN= 00000020 ----------------------------------------- Channel 2 - Device PPE Tx DMA_CCTRL= 00010201 DMA_CDBA= 1e1a6d00 DMA_CIE= 0000000a DMA_CIS= 00000000 DMA_CDLEN= 00000020 ----------------------------------------- Channel 3 - Device PPE Tx DMA_CCTRL= 01010301 DMA_CDBA= 1e1a6d00 DMA_CIE= 00000000 DMA_CIS= 00000004 DMA_CDLEN= 00000020 ----------------------------------------- Channel 4 - Device PPE Tx DMA_CCTRL= 00010401 DMA_CDBA= 1e1a6c00 DMA_CIE= 0000000a DMA_CIS= 00000000 DMA_CDLEN= 00000020 ----------------------------------------- Channel 5 - Device PPE Tx DMA_CCTRL= 00010501 DMA_CDBA= 010f0a00 DMA_CIE= 00000000 DMA_CIS= 0000000e DMA_CDLEN= 00000040 ----------------------------------------- Channel 6 - Device PPE Rx DMA_CCTRL= 00010601 DMA_CDBA= 010f0c00 DMA_CIE= 0000000a DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 7 - Device PPE Tx DMA_CCTRL= 00010700 DMA_CDBA= 010f0e00 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 8 - Device DEU Rx DMA_CCTRL= 00010800 DMA_CDBA= 010f1000 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 9 - Device DEU Tx DMA_CCTRL= 00010900 DMA_CDBA= 010f1200 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 10 - Device DEU Rx DMA_CCTRL= 00010a00 DMA_CDBA= 010f1400 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 11 - Device DEU Tx DMA_CCTRL= 00010b00 DMA_CDBA= 010f1600 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 12 - Device SPI Rx DMA_CCTRL= 00011000 DMA_CDBA= 010f1800 DMA_CIE= 0000000a DMA_CIS= 00000000 DMA_CDLEN= 00000001 ----------------------------------------- Channel 13 - Device SPI Tx DMA_CCTRL= 00011100 DMA_CDBA= 010f1a00 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000001 ----------------------------------------- Channel 14 - Device SDIO Rx DMA_CCTRL= 00011800 DMA_CDBA= 010f1c00 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 15 - Device SDIO Tx DMA_CCTRL= 00011900 DMA_CDBA= 010f1e00 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 16 - Device MCTRL0 Rx DMA_CCTRL= 00012000 DMA_CDBA= 010f2000 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 17 - Device MCTRL0 Tx DMA_CCTRL= 00012100 DMA_CDBA= 010f2200 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 18 - Device MCTRL1 Rx DMA_CCTRL= 00012200 DMA_CDBA= 010f2400 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000040 ----------------------------------------- Channel 19 - Device MCTRL1 Tx DMA_CCTRL= 00012300 DMA_CDBA= 010f2600 DMA_CIE= 00000000 DMA_CIS= 00000000 DMA_CDLEN= 00000040 DMA Port Registers ----------------------------------------- Port 0 DMA_PCTRL= 00001f7c Port 1 DMA_PCTRL= 00001014 Port 2 DMA_PCTRL= 00001014 Port 3 DMA_PCTRL= 00001014 Port 4 DMA_PCTRL= 00001014 Port 5 DMA_PCTRL= 00001014 # # cat /proc/driver/ifx_ssc/reg Register Dump for IFX Synchronous Serial Controller(SSC) SSC0 IFX_SSC_CLC 0x00000100 IFX_SSC_ID 0x08084526 IFX_SSC_MCON 0x005f0230 IFX_SSC_STATE 0x01000003 IFX_SSC_TB 0x00000000 IFX_SSC_FSTAT 0x00000000 IFX_SSC_RXFCON 0x00000401 IFX_SSC_TXFCON 0x00000401 IFX_SSC_BR 0x00000003 IFX_SSC_SFCON 0x00000000 IFX_SSC_SFSTAT 0x00000000 IFX_SSC_GPOCON 0x00000300 IFX_SSC_GPOSTAT 0x0000000b IFX_SSC_RXREQ 0x00000000 IFX_SSC_RXCNT 0x00000000 IFX_SSC_DMACON 0x00000000 IFX_SSC_IRN_EN 0x00000000 IFX_SSC_IRN_CR 0x00000000 IFX_SSC_IRN_ICR 0x00000001 # cat /proc/driver/ifx_cgu/clk_setting pll0 N = 124, M = 8 pll1 N = 64, M = 5, K = 659, modulo = 2 pll0_fosc = 500000000 pll0_fps(1) = 250000000 pll0_fps(2) = 333333333 pll1_fosc = 394715332 pll1_fps = 394715332 pll1_fdiv = 49339417 mips0 clock = 333333333 mips1 clock = 333333333 cpu clock = 333333333 IO region = 166666667 FPI bus 1 = 166666667 FPI bus 2 = 166666667 PP32 clock = 250000000 PCI clock = 22222222 Ethernet MII0= 50000000 Ethernet MII1= 50000000 USB clock = 12000000 Clockout0 = 0 Clockout1 = 0 Clockout2 = 0 Clockout3 = 0 # cat /proc/driver/ifx_gpio/setup IFX GPIO Pin Settings OUT : FEDCBA9876543210 ------------------------- P0: XXX X X P1: X X X P2: X P3: X X ~~~~~~~~~~~~~~~~~~~~~~~~~ IN : FEDCBA9876543210 ------------------------- P0: XXXXXXXXX X XXX P1: XXXXXX XXXXX XX P2: XX XXXXXXXXXXXX P3: XXXXXXXX ~~~~~~~~~~~~~~~~~~~~~~~~~ DIR : FEDCBA9876543210 ------------------------- P0: X X XX XXXX P1: X X XXXX XX P2: XX X P3: X X ~~~~~~~~~~~~~~~~~~~~~~~~~ ALTSEL0: FEDCBA9876543210 ------------------------- P0: X XXXX P1: X X XXX XXX P2: XX P3: ~~~~~~~~~~~~~~~~~~~~~~~~~ ALTSEL1: FEDCBA9876543210 ------------------------- P0: XX X P1: P2: P3: ~~~~~~~~~~~~~~~~~~~~~~~~~ OD : FEDCBA9876543210 ------------------------- P0: XXX XXX XXXX P1: X XXXX XXX P2: XXXXXXXXXXXXXXXX P3: X ~~~~~~~~~~~~~~~~~~~~~~~~~ STOFF : FEDCBA9876543210 ------------------------- P0: P1: P2: P3: ~~~~~~~~~~~~~~~~~~~~~~~~~ PUDSEL : FEDCBA9876543210 ------------------------- P0: X P1: X X X X X P2: X P3: X ~~~~~~~~~~~~~~~~~~~~~~~~~ PUDEN : FEDCBA9876543210 ------------------------- P0: X P1: X X X XX X X P2: X P3: X # cat /proc/driver/ifx_gpio/module IFX GPIO Pin Usage 0 1 2 3 4 5 6 7 ------------------------------------------------------------------------------- P0 Available Available Available Available LEDC LEDC LEDC Available P1 SSC SSC SSC Available Available PCI Available Available P2 PPA Available Available Available Available Available Available Available P3 Available Available Available Available USB HWBUTTON HWBUTTON Available ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 9 10 11 12 13 14 15 ------------------------------------------------------------------------------- P0 Available PPA Available Available Available Available Available Available P1 Available Available Available Available Available USB Available Available P2 Available Available PPA PPA Available Available Available Available P3 N/A N/A N/A N/A N/A N/A N/A N/A # cat /proc/driver/ifx_pmu/pmu PMU Register Dump PMU_PWDCR0(bf10201c) : 0x0201001e PMU_SR0(bf102020) : 0x0201001c Max module number 30 Module 0 USB0-PHY refcnt 2 Module 1 FPI1 refcnt 0 Module 2 DFEV0 refcnt 0 Module 3 DFEV1 refcnt 0 Module 4 PCI refcnt 0 Module 5 DMA refcnt 1 Module 6 USB0-CTRL refcnt 1 Module 7 UART0 refcnt 1 Module 8 SPI refcnt 1 Module 9 DSL-DFE refcnt 0 Module 10 EBU refcnt 0 Module 11 LEDC refcnt 1 Module 12 GPTC refcnt 1 Module 13 VLYNQ refcnt 1 Module 14 FPI0 refcnt 0 Module 15 AHB refcnt 0 Module 16 SDIO refcnt 0 Module 17 UART1 refcnt 0 Module 18 refcnt 0 Module 19 refcnt 0 Module 20 DEU refcnt 0 Module 21 PPE-TC refcnt 0 Module 22 PPE-EMA refcnt 1 Module 23 PPE-DPLUS refcnt 1 Module 24 DDR-MEM refcnt 0 Module 25 TDM refcnt 0 Module 26 USB1-PHY refcnt 2 Module 27 USB1-CTRL refcnt 1 Module 28 SWITCH refcnt 1 Module 29 DDR-DPD refcnt 1 # cat /proc/driver/ifx_dma/g_desc_list channel 0 PPE Rx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f0000 01edb060 80000620 D c s e 0 <- PREV 1 0xa10f0008 01ef8860 80000620 D c s e 0 2 0xa10f0010 01e91060 80000620 D c s e 0 <- CURR 3 0xa10f0018 01e92860 80000620 D c s e 0 4 0xa10f0020 01e92060 80000620 D c s e 0 5 0xa10f0028 01e93860 80000620 D c s e 0 6 0xa10f0030 01e93060 80000620 D c s e 0 7 0xa10f0038 01e94860 80000620 D c s e 0 8 0xa10f0040 01e94060 80000620 D c s e 0 9 0xa10f0048 01e95860 80000620 D c s e 0 10 0xa10f0050 01e95060 80000620 D c s e 0 11 0xa10f0058 01e96860 80000620 D c s e 0 12 0xa10f0060 01e96060 80000620 D c s e 0 13 0xa10f0068 01e97860 80000620 D c s e 0 14 0xa10f0070 01e97060 80000620 D c s e 0 15 0xa10f0078 01e98860 80000620 D c s e 0 16 0xa10f0080 01e98060 80000620 D c s e 0 17 0xa10f0088 01e9a860 80000620 D c s e 0 18 0xa10f0090 01e9a060 80000620 D c s e 0 19 0xa10f0098 01e9b860 80000620 D c s e 0 20 0xa10f00a0 01e9b060 80000620 D c s e 0 21 0xa10f00a8 01e9c860 80000620 D c s e 0 22 0xa10f00b0 01e9c060 80000620 D c s e 0 23 0xa10f00b8 01e9d860 80000620 D c s e 0 24 0xa10f00c0 01e9d060 80000620 D c s e 0 25 0xa10f00c8 01e9e860 80000620 D c s e 0 26 0xa10f00d0 01e9e060 80000620 D c s e 0 27 0xa10f00d8 01e9f860 80000620 D c s e 0 28 0xa10f00e0 01e9f060 80000620 D c s e 0 29 0xa10f00e8 01ea0860 80000620 D c s e 0 30 0xa10f00f0 01ea0060 80000620 D c s e 0 31 0xa10f00f8 01ea1860 80000620 D c s e 0 32 0xa10f0100 01ea1060 80000620 D c s e 0 33 0xa10f0108 01ea2860 80000620 D c s e 0 34 0xa10f0110 01ea2060 80000620 D c s e 0 35 0xa10f0118 01ea3860 80000620 D c s e 0 36 0xa10f0120 01ea3060 80000620 D c s e 0 37 0xa10f0128 01ea5860 80000620 D c s e 0 38 0xa10f0130 01ea5060 80000620 D c s e 0 39 0xa10f0138 01ea6860 80000620 D c s e 0 40 0xa10f0140 01ea6060 80000620 D c s e 0 41 0xa10f0148 01ea7860 80000620 D c s e 0 42 0xa10f0150 01ea7060 80000620 D c s e 0 43 0xa10f0158 01ea8860 80000620 D c s e 0 44 0xa10f0160 01ea8060 80000620 D c s e 0 45 0xa10f0168 01ea9860 80000620 D c s e 0 46 0xa10f0170 01ea9060 80000620 D c s e 0 47 0xa10f0178 01eaa860 80000620 D c s e 0 48 0xa10f0180 01eaa060 80000620 D c s e 0 49 0xa10f0188 01eac860 80000620 D c s e 0 50 0xa10fchannel 1 PPE Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xbe1a6c00 01e7d060 b0000620 D c S E 00 <- CURR<- PREV 1 0xbe1a6c08 01e7e860 b0000620 D c S E 00 2 0xbe1a6c10 01e7e060 b0000620 D c S E 00 3 0xbe1a6c18 01e7f860 b0000620 D c S E 00 4 0xbe1a6c20 01e7f060 b0000620 D c S E 00 5 0xbe1a6c28 01e80860 b0000620 D c S E 00 6 0xbe1a6c30 01e80060 b0000620 D c S E 00 7 0xbe1a6c38 01e81860 b0000620 D c S E 00 8 0xbe1a6c40 01e81060 b0000620 D c S E 00 9 0xbe1a6c48 01e83860 b0000620 D c S E 00 10 0xbe1a6c50 01e83060 b0000620 D c S E 00 11 0xbe1a6c58 01e84860 b0000620 D c S E 00 12 0xbe1a6c60 01e84060 b0000620 D c S E 00 13 0xbe1a6c68 01e85860 b0000620 D c S E 00 14 0xbe1a6c70 01e85060 b0000620 D c S E 00 15 0xbe1a6c78 01e86860 b0000620 D c S E 00 16 0xbe1a6c80 01e86060 b0000620 D c S E 00 17 0xbe1a6c88 01e87860 b0000620 D c S E 00 18 0xbe1a6c90 01e87060 b0000620 D c S E 00 19 0xbe1a6c98 01e88860 b0000620 D c S E 00 20 0xbe1a6ca0 01e88060 b0000620 D c S E 00 21 0xbe1a6ca8 01e8a860 b0000620 D c S E 00 22 0xbe1a6cb0 01e8a060 b0000620 D c S E 00 23 0xbe1a6cb8 01e8b860 b0000620 D c S E 00 24 0xbe1a6cc0 01e8b060 b0000620 D c S E 00 25 0xbe1a6cc8 01e8c860 b0000620 D c S E 00 26 0xbe1a6cd0 01e8c060 b0000620 D c S E 00 27 0xbe1a6cd8 01e8d860 b0000620 D c S E 00 28 0xbe1a6ce0 01e8d060 b0000620 D c S E 00 29 0xbe1a6ce8 01e8f860 b0000620 D c S E 00 30 0xbe1a6cf0 01e8f060 b0000620 D c S E 00 31 0xbe1a6cf8 01e90860 b0000620 D c S E 00 channel 2 PPE Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xbe1a6d00 01e76060 80000620 D c s e 00 <- CURR<- PREV 1 0xbe1a6d08 01e7b860 80000620 D c s e 00 2 0xbe1a6d10 01e7b060 80000620 D c s e 00 3 0xbe1a6d18 01e16860 80000620 D c s e 00 4 0xbe1a6d20 01e16060 80000620 D c s e 00 5 0xbe1a6d28 01e17860 80000620 D c s e 00 6 0xbe1a6d30 01e17060 80000620 D c s e 00 7 0xbe1a6d38 003fa860 80000620 D c s e 00 8 0xbe1a6d40 003fa060 80000620 D c s e 00 9 0xbe1a6d48 003fb860 80000620 D c s e 00 10 0xbe1a6d50 003fb060 80000620 D c s e 00 11 0xbe1a6d58 003ce860 80000620 D c s e 00 12 0xbe1a6d60 003ce060 80000620 D c s e 00 13 0xbe1a6d68 003cf860 80000620 D c s e 00 14 0xbe1a6d70 003cf060 80000620 D c s e 00 15 0xbe1a6d78 003dc860 80000620 D c s e 00 16 0xbe1a6d80 003dc060 80000620 D c s e 00 17 0xbe1a6d88 003dd860 80000620 D c s e 00 18 0xbe1a6d90 003dd060 80000620 D c s e 00 19 0xbe1a6d98 003da860 80000620 D c s e 00 20 0xbe1a6da0 003da060 80000620 D c s e 00 21 0xbe1a6da8 003e8860 80000620 D c s e 00 22 0xbe1a6db0 003e8060 80000620 D c s e 00 23 0xbe1a6db8 003e9860 80000620 D c s e 00 24 0xbe1a6dc0 003e9060 80000620 D c s e 00 25 0xbe1a6dc8 003ea860 80000620 D c s e 00 26 0xbe1a6dd0 003ea060 80000620 D c s e 00 27 0xbe1a6dd8 003eb860 80000620 D c s e 00 28 0xbe1a6de0 003eb060 80000620 D c s e 00 29 0xbe1a6de8 01e7c860 80000620 D c s e 00 30 0xbe1a6df0 01e7c060 80000620 D c s e 00 31 0xbe1a6df8 01e7d860 80000620 D c s e 00 channel 3 PPE Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xbe1a6d00 01e76060 80000620 D c s e 00 <- CURR<- PREV 1 0xbe1a6d08 01e7b860 80000620 D c s e 00 2 0xbe1a6d10 01e7b060 80000620 D c s e 00 3 0xbe1a6d18 01e16860 80000620 D c s e 00 4 0xbe1a6d20 01e16060 80000620 D c s e 00 5 0xbe1a6d28 01e17860 80000620 D c s e 00 6 0xbe1a6d30 01e17060 80000620 D c s e 00 7 0xbe1a6d38 003fa860 80000620 D c s e 00 8 0xbe1a6d40 003fa060 80000620 D c s e 00 9 0xbe1a6d48 003fb860 80000620 D c s e 00 10 0xbe1a6d50 003fb060 80000620 D c s e 00 11 0xbe1a6d58 003ce860 80000620 D c s e 00 12 0xbe1a6d60 003ce060 80000620 D c s e 00 13 0xbe1a6d68 003cf860 80000620 D c s e 00 14 0xbe1a6d70 003cf060 80000620 D c s e 00 15 0xbe1a6d78 003dc860 80000620 D c s e 00 16 0xbe1a6d80 003dc060 80000620 D c s e 00 17 0xbe1a6d88 003dd860 80000620 D c s e 00 18 0xbe1a6d90 003dd060 80000620 D c s e 00 19 0xbe1a6d98 003da860 80000620 D c s e 00 20 0xbe1a6da0 003da060 80000620 D c s e 00 21 0xbe1a6da8 003e8860 80000620 D c s e 00 22 0xbe1a6db0 003e8060 80000620 D c s e 00 23 0xbe1a6db8 003e9860 80000620 D c s e 00 24 0xbe1a6dc0 003e9060 80000620 D c s e 00 25 0xbe1a6dc8 003ea860 80000620 D c s e 00 26 0xbe1a6dd0 003ea060 80000620 D c s e 00 27 0xbe1a6dd8 003eb860 80000620 D c s e 00 28 0xbe1a6de0 003eb060 80000620 D c s e 00 29 0xbe1a6de8 01e7c860 80000620 D c s e 00 30 0xbe1a6df0 01e7c060 80000620 D c s e 00 31 0xbe1a6df8 01e7d860 80000620 D c s e 00 channel 4 PPE Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xbe1a6c00 01e7d060 b0000620 D c S E 00 <- CURR<- PREV 1 0xbe1a6c08 01e7e860 b0000620 D c S E 00 2 0xbe1a6c10 01e7e060 b0000620 D c S E 00 3 0xbe1a6c18 01e7f860 b0000620 D c S E 00 4 0xbe1a6c20 01e7f060 b0000620 D c S E 00 5 0xbe1a6c28 01e80860 b0000620 D c S E 00 6 0xbe1a6c30 01e80060 b0000620 D c S E 00 7 0xbe1a6c38 01e81860 b0000620 D c S E 00 8 0xbe1a6c40 01e81060 b0000620 D c S E 00 9 0xbe1a6c48 01e83860 b0000620 D c S E 00 10 0xbe1a6c50 01e83060 b0000620 D c S E 00 11 0xbe1a6c58 01e84860 b0000620 D c S E 00 12 0xbe1a6c60 01e84060 b0000620 D c S E 00 13 0xbe1a6c68 01e85860 b0000620 D c S E 00 14 0xbe1a6c70 01e85060 b0000620 D c S E 00 15 0xbe1a6c78 01e86860 b0000620 D c S E 00 16 0xbe1a6c80 01e86060 b0000620 D c S E 00 17 0xbe1a6c88 01e87860 b0000620 D c S E 00 18 0xbe1a6c90 01e87060 b0000620 D c S E 00 19 0xbe1a6c98 01e88860 b0000620 D c S E 00 20 0xbe1a6ca0 01e88060 b0000620 D c S E 00 21 0xbe1a6ca8 01e8a860 b0000620 D c S E 00 22 0xbe1a6cb0 01e8a060 b0000620 D c S E 00 23 0xbe1a6cb8 01e8b860 b0000620 D c S E 00 24 0xbe1a6cc0 01e8b060 b0000620 D c S E 00 25 0xbe1a6cc8 01e8c860 b0000620 D c S E 00 26 0xbe1a6cd0 01e8c060 b0000620 D c S E 00 27 0xbe1a6cd8 01e8d860 b0000620 D c S E 00 28 0xbe1a6ce0 01e8d060 b0000620 D c S E 00 29 0xbe1a6ce8 01e8f860 b0000620 D c S E 00 30 0xbe1a6cf0 01e8f060 b0000620 D c S E 00 31 0xbe1a6cf8 01e90860 b0000620 D c S E 00 channel 5 PPE Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f0a00 00000000 00000000 C c s e 00 1 0xa10f0a08 00000000 00000000 C c s e 00 2 0xa10f0a10 00000000 00000000 C c s e 00 3 0xa10f0a18 00000000 00000000 C c s e 00 4 0xa10f0a20 00000000 00000000 C c s e 00 5 0xa10f0a28 00000000 00000000 C c s e 00 6 0xa10f0a30 00000000 00000000 C c s e 00 7 0xa10f0a38 00000000 00000000 C c s e 00 8 0xa10f0a40 00000000 00000000 C c s e 00 9 0xa10f0a48 00000000 00000000 C c s e 00 10 0xa10f0a50 00000000 00000000 C c s e 00 11 0xa10f0a58 00000000 00000000 C c s e 00 12 0xa10f0a60 00000000 00000000 C c s e 00 13 0xa10f0a68 00000000 00000000 C c s e 00 14 0xa10f0a70 00000000 00000000 C c s e 00 15 0xa10f0a78 00000000 00000000 C c s e 00 16 0xa10f0a80 00000000 00000000 C c s e 00 17 0xa10f0a88 00000000 00000000 C c s e 00 18 0xa10f0a90 00000000 00000000 C c s e 00 19 0xa10f0a98 00000000 00000000 C c s e 00 20 0xa10f0aa0 00000000 00000000 C c s e 00 21 0xa10f0aa8 00000000 00000000 C c s e 00 22 0xa10f0ab0 00000000 00000000 C c s e 00 23 0xa10f0ab8 00000000 00000000 C c s e 00 24 0xa10f0ac0 00000000 00000000 C c s e 00 25 0xa10f0ac8 00000000 00000000 C c s e 00 26 0xa10f0ad0 00000000 00000000 C c s e 00 27 0xa10f0ad8 00000000 00000000 C c s e 00 28 0xa10f0ae0 00000000 00000000 C c s e 00 29 0xa10f0ae8 00000000 00000000 C c s e 00 30 0xa10f0af0 00000000 00000000 C c s e 00 31 0xa10f0af8 00000000 00000000 C c s e 00 32 0xa10f0b00 00000000 00000000 C c s e 00 33 0xa10f0b08 00000000 00000000 C c s e 00 34 0xa10f0b10 00000000 00000000 C c s e 00 35 0xa10f0b18 00000000 00000000 C c s e 00 36 0xa10f0b20 00000000 00000000 C c s e 00 37 0xa10f0b28 00000000 00000000 C c s e 00 38 0xa10f0b30 00000000 00000000 C c s e 00 39 0xa10f0b38 00000000 00000000 C c s e 00 40 0xa10f0b40 00000000 00000000 C c s e 00 41 0xa10f0b48 00000000 00000000 C c s e 00 42 0xa10f0b50 00000000 00000000 C c s e 00 43 0xa10f0b58 00000000 00000000 C c s e 00 44 0xa10f0b60 00000000 00000000 C c s e 00 45 0xa10f0b68 01e91880 71000000 C C S E 02 <- PREV 46 0xa10f0b70 00000000 00000000 C c s e 00 <- CURR 47 0xa10f0b78 00000000 00000000 C c s e 00 48 0xa10f0b80 00000000 00000000 C c s e 00 49 0xa10f0b88 channel 6 PPE Rx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f0c00 01ef6860 80000620 D c s e 0 <- PREV 1 0xa10f0c08 01ee2060 80000620 D c s e 0 2 0xa10f0c10 01ee7060 80000620 D c s e 0 3 0xa10f0c18 01ee1860 80000620 D c s e 0 4 0xa10f0c20 01ee3860 80000620 D c s e 0 5 0xa10f0c28 01ee9060 80000620 D c s e 0 6 0xa10f0c30 01bcb860 80000620 D c s e 0 7 0xa10f0c38 01ee3060 80000620 D c s e 0 8 0xa10f0c40 01ee7860 80000620 D c s e 0 9 0xa10f0c48 01ee5060 80000620 D c s e 0 10 0xa10f0c50 01ef8060 80000620 D c s e 0 11 0xa10f0c58 01ee6860 80000620 D c s e 0 12 0xa10f0c60 01eec060 80000620 D c s e 0 13 0xa10f0c68 01eea060 80000620 D c s e 0 14 0xa10f0c70 015a9860 80000620 D c s e 0 15 0xa10f0c78 015a9060 80000620 D c s e 0 16 0xa10f0c80 013f8860 80000620 D c s e 0 17 0xa10f0c88 019e9060 80000620 D c s e 0 18 0xa10f0c90 01eea860 80000620 D c s e 0 19 0xa10f0c98 01ee9860 80000620 D c s e 0 20 0xa10f0ca0 01eee060 80000620 D c s e 0 21 0xa10f0ca8 01ee5860 80000620 D c s e 0 22 0xa10f0cb0 01ef2060 80000620 D c s e 0 23 0xa10f0cb8 01ef5060 80000620 D c s e 0 24 0xa10f0cc0 01ef3060 80000620 D c s e 0 25 0xa10f0cc8 01eda060 80000620 D c s e 0 26 0xa10f0cd0 01ef1060 80000620 D c s e 0 27 0xa10f0cd8 01e91860 80000620 D c s e 0 28 0xa10f0ce0 01ef0060 80000620 D c s e 0 <- CURR 29 0xa10f0ce8 013d7860 80000620 D c s e 0 30 0xa10f0cf0 013d5860 80000620 D c s e 0 31 0xa10f0cf8 019e9860 80000620 D c s e 0 32 0xa10f0d00 01ef0860 80000620 D c s e 0 33 0xa10f0d08 01eee860 80000620 D c s e 0 34 0xa10f0d10 01ef9060 80000620 D c s e 0 35 0xa10f0d18 01ef3860 80000620 D c s e 0 36 0xa10f0d20 01eeb060 80000620 D c s e 0 37 0xa10f0d28 01ef5860 80000620 D c s e 0 38 0xa10f0d30 0138c860 80000620 D c s e 0 39 0xa10f0d38 01ef2860 80000620 D c s e 0 40 0xa10f0d40 01ee4860 80000620 D c s e 0 41 0xa10f0d48 01ef9860 80000620 D c s e 0 42 0xa10f0d50 01ef6060 80000620 D c s e 0 43 0xa10f0d58 01efb860 80000620 D c s e 0 44 0xa10f0d60 01efb060 80000620 D c s e 0 45 0xa10f0d68 01efc860 80000620 D c s e 0 46 0xa10f0d70 01efa060 80000620 D c s e 0 47 0xa10f0d78 01ede060 80000620 D c s e 0 48 0xa10f0d80 014bd860 80000620 D c s e 0 49 0xa10f0d88 01ede860 80000620 D c s e 0 50 0xa10fchannel 7 PPE Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f0e00 00000000 00000000 C c s e 00 <- CURR<- PREV 1 0xa10f0e08 00000000 00000000 C c s e 00 2 0xa10f0e10 00000000 00000000 C c s e 00 3 0xa10f0e18 00000000 00000000 C c s e 00 4 0xa10f0e20 00000000 00000000 C c s e 00 5 0xa10f0e28 00000000 00000000 C c s e 00 6 0xa10f0e30 00000000 00000000 C c s e 00 7 0xa10f0e38 00000000 00000000 C c s e 00 8 0xa10f0e40 00000000 00000000 C c s e 00 9 0xa10f0e48 00000000 00000000 C c s e 00 10 0xa10f0e50 00000000 00000000 C c s e 00 11 0xa10f0e58 00000000 00000000 C c s e 00 12 0xa10f0e60 00000000 00000000 C c s e 00 13 0xa10f0e68 00000000 00000000 C c s e 00 14 0xa10f0e70 00000000 00000000 C c s e 00 15 0xa10f0e78 00000000 00000000 C c s e 00 16 0xa10f0e80 00000000 00000000 C c s e 00 17 0xa10f0e88 00000000 00000000 C c s e 00 18 0xa10f0e90 00000000 00000000 C c s e 00 19 0xa10f0e98 00000000 00000000 C c s e 00 20 0xa10f0ea0 00000000 00000000 C c s e 00 21 0xa10f0ea8 00000000 00000000 C c s e 00 22 0xa10f0eb0 00000000 00000000 C c s e 00 23 0xa10f0eb8 00000000 00000000 C c s e 00 24 0xa10f0ec0 00000000 00000000 C c s e 00 25 0xa10f0ec8 00000000 00000000 C c s e 00 26 0xa10f0ed0 00000000 00000000 C c s e 00 27 0xa10f0ed8 00000000 00000000 C c s e 00 28 0xa10f0ee0 00000000 00000000 C c s e 00 29 0xa10f0ee8 00000000 00000000 C c s e 00 30 0xa10f0ef0 00000000 00000000 C c s e 00 31 0xa10f0ef8 00000000 00000000 C c s e 00 32 0xa10f0f00 00000000 00000000 C c s e 00 33 0xa10f0f08 00000000 00000000 C c s e 00 34 0xa10f0f10 00000000 00000000 C c s e 00 35 0xa10f0f18 00000000 00000000 C c s e 00 36 0xa10f0f20 00000000 00000000 C c s e 00 37 0xa10f0f28 00000000 00000000 C c s e 00 38 0xa10f0f30 00000000 00000000 C c s e 00 39 0xa10f0f38 00000000 00000000 C c s e 00 40 0xa10f0f40 00000000 00000000 C c s e 00 41 0xa10f0f48 00000000 00000000 C c s e 00 42 0xa10f0f50 00000000 00000000 C c s e 00 43 0xa10f0f58 00000000 00000000 C c s e 00 44 0xa10f0f60 00000000 00000000 C c s e 00 45 0xa10f0f68 00000000 00000000 C c s e 00 46 0xa10f0f70 00000000 00000000 C c s e 00 47 0xa10f0f78 00000000 00000000 C c s e 00 48 0xa10f0f80 00000000 00000000 C c s e 00 49 0xa10f0f88 channel 8 DEU Rx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f1000 00000000 00000000 C c s e 0 <- CURR<- PREV 1 0xa10f1008 00000000 00000000 C c s e 0 2 0xa10f1010 00000000 00000000 C c s e 0 3 0xa10f1018 00000000 00000000 C c s e 0 4 0xa10f1020 00000000 00000000 C c s e 0 5 0xa10f1028 00000000 00000000 C c s e 0 6 0xa10f1030 00000000 00000000 C c s e 0 7 0xa10f1038 00000000 00000000 C c s e 0 8 0xa10f1040 00000000 00000000 C c s e 0 9 0xa10f1048 00000000 00000000 C c s e 0 10 0xa10f1050 00000000 00000000 C c s e 0 11 0xa10f1058 00000000 00000000 C c s e 0 12 0xa10f1060 00000000 00000000 C c s e 0 13 0xa10f1068 00000000 00000000 C c s e 0 14 0xa10f1070 00000000 00000000 C c s e 0 15 0xa10f1078 00000000 00000000 C c s e 0 16 0xa10f1080 00000000 00000000 C c s e 0 17 0xa10f1088 00000000 00000000 C c s e 0 18 0xa10f1090 00000000 00000000 C c s e 0 19 0xa10f1098 00000000 00000000 C c s e 0 20 0xa10f10a0 00000000 00000000 C c s e 0 21 0xa10f10a8 00000000 00000000 C c s e 0 22 0xa10f10b0 00000000 00000000 C c s e 0 23 0xa10f10b8 00000000 00000000 C c s e 0 24 0xa10f10c0 00000000 00000000 C c s e 0 25 0xa10f10c8 00000000 00000000 C c s e 0 26 0xa10f10d0 00000000 00000000 C c s e 0 27 0xa10f10d8 00000000 00000000 C c s e 0 28 0xa10f10e0 00000000 00000000 C c s e 0 29 0xa10f10e8 00000000 00000000 C c s e 0 30 0xa10f10f0 00000000 00000000 C c s e 0 31 0xa10f10f8 00000000 00000000 C c s e 0 32 0xa10f1100 00000000 00000000 C c s e 0 33 0xa10f1108 00000000 00000000 C c s e 0 34 0xa10f1110 00000000 00000000 C c s e 0 35 0xa10f1118 00000000 00000000 C c s e 0 36 0xa10f1120 00000000 00000000 C c s e 0 37 0xa10f1128 00000000 00000000 C c s e 0 38 0xa10f1130 00000000 00000000 C c s e 0 39 0xa10f1138 00000000 00000000 C c s e 0 40 0xa10f1140 00000000 00000000 C c s e 0 41 0xa10f1148 00000000 00000000 C c s e 0 42 0xa10f1150 00000000 00000000 C c s e 0 43 0xa10f1158 00000000 00000000 C c s e 0 44 0xa10f1160 00000000 00000000 C c s e 0 45 0xa10f1168 00000000 00000000 C c s e 0 46 0xa10f1170 00000000 00000000 C c s e 0 47 0xa10f1178 00000000 00000000 C c s e 0 48 0xa10f1180 00000000 00000000 C c s e 0 49 0xa10f1188 00000000 00000000 C c s e 0 50 0xa10fchannel 9 DEU Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f1200 00000000 00000000 C c s e 00 <- CURR<- PREV 1 0xa10f1208 00000000 00000000 C c s e 00 2 0xa10f1210 00000000 00000000 C c s e 00 3 0xa10f1218 00000000 00000000 C c s e 00 4 0xa10f1220 00000000 00000000 C c s e 00 5 0xa10f1228 00000000 00000000 C c s e 00 6 0xa10f1230 00000000 00000000 C c s e 00 7 0xa10f1238 00000000 00000000 C c s e 00 8 0xa10f1240 00000000 00000000 C c s e 00 9 0xa10f1248 00000000 00000000 C c s e 00 10 0xa10f1250 00000000 00000000 C c s e 00 11 0xa10f1258 00000000 00000000 C c s e 00 12 0xa10f1260 00000000 00000000 C c s e 00 13 0xa10f1268 00000000 00000000 C c s e 00 14 0xa10f1270 00000000 00000000 C c s e 00 15 0xa10f1278 00000000 00000000 C c s e 00 16 0xa10f1280 00000000 00000000 C c s e 00 17 0xa10f1288 00000000 00000000 C c s e 00 18 0xa10f1290 00000000 00000000 C c s e 00 19 0xa10f1298 00000000 00000000 C c s e 00 20 0xa10f12a0 00000000 00000000 C c s e 00 21 0xa10f12a8 00000000 00000000 C c s e 00 22 0xa10f12b0 00000000 00000000 C c s e 00 23 0xa10f12b8 00000000 00000000 C c s e 00 24 0xa10f12c0 00000000 00000000 C c s e 00 25 0xa10f12c8 00000000 00000000 C c s e 00 26 0xa10f12d0 00000000 00000000 C c s e 00 27 0xa10f12d8 00000000 00000000 C c s e 00 28 0xa10f12e0 00000000 00000000 C c s e 00 29 0xa10f12e8 00000000 00000000 C c s e 00 30 0xa10f12f0 00000000 00000000 C c s e 00 31 0xa10f12f8 00000000 00000000 C c s e 00 32 0xa10f1300 00000000 00000000 C c s e 00 33 0xa10f1308 00000000 00000000 C c s e 00 34 0xa10f1310 00000000 00000000 C c s e 00 35 0xa10f1318 00000000 00000000 C c s e 00 36 0xa10f1320 00000000 00000000 C c s e 00 37 0xa10f1328 00000000 00000000 C c s e 00 38 0xa10f1330 00000000 00000000 C c s e 00 39 0xa10f1338 00000000 00000000 C c s e 00 40 0xa10f1340 00000000 00000000 C c s e 00 41 0xa10f1348 00000000 00000000 C c s e 00 42 0xa10f1350 00000000 00000000 C c s e 00 43 0xa10f1358 00000000 00000000 C c s e 00 44 0xa10f1360 00000000 00000000 C c s e 00 45 0xa10f1368 00000000 00000000 C c s e 00 46 0xa10f1370 00000000 00000000 C c s e 00 47 0xa10f1378 00000000 00000000 C c s e 00 48 0xa10f1380 00000000 00000000 C c s e 00 49 0xa10f1388 channel 10 DEU Rx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f1400 00000000 00000000 C c s e 0 <- CURR<- PREV 1 0xa10f1408 00000000 00000000 C c s e 0 2 0xa10f1410 00000000 00000000 C c s e 0 3 0xa10f1418 00000000 00000000 C c s e 0 4 0xa10f1420 00000000 00000000 C c s e 0 5 0xa10f1428 00000000 00000000 C c s e 0 6 0xa10f1430 00000000 00000000 C c s e 0 7 0xa10f1438 00000000 00000000 C c s e 0 8 0xa10f1440 00000000 00000000 C c s e 0 9 0xa10f1448 00000000 00000000 C c s e 0 10 0xa10f1450 00000000 00000000 C c s e 0 11 0xa10f1458 00000000 00000000 C c s e 0 12 0xa10f1460 00000000 00000000 C c s e 0 13 0xa10f1468 00000000 00000000 C c s e 0 14 0xa10f1470 00000000 00000000 C c s e 0 15 0xa10f1478 00000000 00000000 C c s e 0 16 0xa10f1480 00000000 00000000 C c s e 0 17 0xa10f1488 00000000 00000000 C c s e 0 18 0xa10f1490 00000000 00000000 C c s e 0 19 0xa10f1498 00000000 00000000 C c s e 0 20 0xa10f14a0 00000000 00000000 C c s e 0 21 0xa10f14a8 00000000 00000000 C c s e 0 22 0xa10f14b0 00000000 00000000 C c s e 0 23 0xa10f14b8 00000000 00000000 C c s e 0 24 0xa10f14c0 00000000 00000000 C c s e 0 25 0xa10f14c8 00000000 00000000 C c s e 0 26 0xa10f14d0 00000000 00000000 C c s e 0 27 0xa10f14d8 00000000 00000000 C c s e 0 28 0xa10f14e0 00000000 00000000 C c s e 0 29 0xa10f14e8 00000000 00000000 C c s e 0 30 0xa10f14f0 00000000 00000000 C c s e 0 31 0xa10f14f8 00000000 00000000 C c s e 0 32 0xa10f1500 00000000 00000000 C c s e 0 33 0xa10f1508 00000000 00000000 C c s e 0 34 0xa10f1510 00000000 00000000 C c s e 0 35 0xa10f1518 00000000 00000000 C c s e 0 36 0xa10f1520 00000000 00000000 C c s e 0 37 0xa10f1528 00000000 00000000 C c s e 0 38 0xa10f1530 00000000 00000000 C c s e 0 39 0xa10f1538 00000000 00000000 C c s e 0 40 0xa10f1540 00000000 00000000 C c s e 0 41 0xa10f1548 00000000 00000000 C c s e 0 42 0xa10f1550 00000000 00000000 C c s e 0 43 0xa10f1558 00000000 00000000 C c s e 0 44 0xa10f1560 00000000 00000000 C c s e 0 45 0xa10f1568 00000000 00000000 C c s e 0 46 0xa10f1570 00000000 00000000 C c s e 0 47 0xa10f1578 00000000 00000000 C c s e 0 48 0xa10f1580 00000000 00000000 C c s e 0 49 0xa10f1588 00000000 00000000 C c s e 0 50 0xa10channel 11 DEU Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f1600 00000000 00000000 C c s e 00 <- CURR<- PREV 1 0xa10f1608 00000000 00000000 C c s e 00 2 0xa10f1610 00000000 00000000 C c s e 00 3 0xa10f1618 00000000 00000000 C c s e 00 4 0xa10f1620 00000000 00000000 C c s e 00 5 0xa10f1628 00000000 00000000 C c s e 00 6 0xa10f1630 00000000 00000000 C c s e 00 7 0xa10f1638 00000000 00000000 C c s e 00 8 0xa10f1640 00000000 00000000 C c s e 00 9 0xa10f1648 00000000 00000000 C c s e 00 10 0xa10f1650 00000000 00000000 C c s e 00 11 0xa10f1658 00000000 00000000 C c s e 00 12 0xa10f1660 00000000 00000000 C c s e 00 13 0xa10f1668 00000000 00000000 C c s e 00 14 0xa10f1670 00000000 00000000 C c s e 00 15 0xa10f1678 00000000 00000000 C c s e 00 16 0xa10f1680 00000000 00000000 C c s e 00 17 0xa10f1688 00000000 00000000 C c s e 00 18 0xa10f1690 00000000 00000000 C c s e 00 19 0xa10f1698 00000000 00000000 C c s e 00 20 0xa10f16a0 00000000 00000000 C c s e 00 21 0xa10f16a8 00000000 00000000 C c s e 00 22 0xa10f16b0 00000000 00000000 C c s e 00 23 0xa10f16b8 00000000 00000000 C c s e 00 24 0xa10f16c0 00000000 00000000 C c s e 00 25 0xa10f16c8 00000000 00000000 C c s e 00 26 0xa10f16d0 00000000 00000000 C c s e 00 27 0xa10f16d8 00000000 00000000 C c s e 00 28 0xa10f16e0 00000000 00000000 C c s e 00 29 0xa10f16e8 00000000 00000000 C c s e 00 30 0xa10f16f0 00000000 00000000 C c s e 00 31 0xa10f16f8 00000000 00000000 C c s e 00 32 0xa10f1700 00000000 00000000 C c s e 00 33 0xa10f1708 00000000 00000000 C c s e 00 34 0xa10f1710 00000000 00000000 C c s e 00 35 0xa10f1718 00000000 00000000 C c s e 00 36 0xa10f1720 00000000 00000000 C c s e 00 37 0xa10f1728 00000000 00000000 C c s e 00 38 0xa10f1730 00000000 00000000 C c s e 00 39 0xa10f1738 00000000 00000000 C c s e 00 40 0xa10f1740 00000000 00000000 C c s e 00 41 0xa10f1748 00000000 00000000 C c s e 00 42 0xa10f1750 00000000 00000000 C c s e 00 43 0xa10f1758 00000000 00000000 C c s e 00 44 0xa10f1760 00000000 00000000 C c s e 00 45 0xa10f1768 00000000 00000000 C c s e 00 46 0xa10f1770 00000000 00000000 C c s e 00 47 0xa10f1778 00000000 00000000 C c s e 00 48 0xa10f1780 00000000 00000000 C c s e 00 49 0xa10f1788 channel 12 SPI Rx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f1800 00000000 00000000 C c s e 0 <- CURR<- PREV channel 13 SPI Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f1a00 00000000 00000000 C c s e 00 <- CURR<- PREV channel 14 SDIO Rx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f1c00 00000000 00000000 C c s e 0 <- CURR<- PREV 1 0xa10f1c08 00000000 00000000 C c s e 0 2 0xa10f1c10 00000000 00000000 C c s e 0 3 0xa10f1c18 00000000 00000000 C c s e 0 4 0xa10f1c20 00000000 00000000 C c s e 0 5 0xa10f1c28 00000000 00000000 C c s e 0 6 0xa10f1c30 00000000 00000000 C c s e 0 7 0xa10f1c38 00000000 00000000 C c s e 0 8 0xa10f1c40 00000000 00000000 C c s e 0 9 0xa10f1c48 00000000 00000000 C c s e 0 10 0xa10f1c50 00000000 00000000 C c s e 0 11 0xa10f1c58 00000000 00000000 C c s e 0 12 0xa10f1c60 00000000 00000000 C c s e 0 13 0xa10f1c68 00000000 00000000 C c s e 0 14 0xa10f1c70 00000000 00000000 C c s e 0 15 0xa10f1c78 00000000 00000000 C c s e 0 16 0xa10f1c80 00000000 00000000 C c s e 0 17 0xa10f1c88 00000000 00000000 C c s e 0 18 0xa10f1c90 00000000 00000000 C c s e 0 19 0xa10f1c98 00000000 00000000 C c s e 0 20 0xa10f1ca0 00000000 00000000 C c s e 0 21 0xa10f1ca8 00000000 00000000 C c s e 0 22 0xa10f1cb0 00000000 00000000 C c s e 0 23 0xa10f1cb8 00000000 00000000 C c s e 0 24 0xa10f1cc0 00000000 00000000 C c s e 0 25 0xa10f1cc8 00000000 00000000 C c s e 0 26 0xa10f1cd0 00000000 00000000 C c s e 0 27 0xa10f1cd8 00000000 00000000 C c s e 0 28 0xa10f1ce0 00000000 00000000 C c s e 0 29 0xa10f1ce8 00000000 00000000 C c s e 0 30 0xa10f1cf0 00000000 00000000 C c s e 0 31 0xa10f1cf8 00000000 00000000 C c s e 0 32 0xa10f1d00 00000000 00000000 C c s e 0 33 0xa10f1d08 00000000 00000000 C c s e 0 34 0xa10f1d10 00000000 00000000 C c s e 0 35 0xa10f1d18 00000000 00000000 C c s e 0 36 0xa10f1d20 00000000 00000000 C c s e 0 37 0xa10f1d28 00000000 00000000 C c s e 0 38 0xa10f1d30 00000000 00000000 C c s e 0 39 0xa10f1d38 00000000 00000000 C c s e 0 40 0xa10f1d40 00000000 00000000 C c s e 0 41 0xa10f1d48 00000000 00000000 C c s e 0 42 0xa10f1d50 00000000 00000000 C c s e 0 43 0xa10f1d58 00000000 00000000 C c s e 0 44 0xa10f1d60 00000000 00000000 C c s e 0 45 0xa10f1d68 00000000 00000000 C c s e 0 46 0xa10f1d70 00000000 00000000 C c s e 0 47 0xa10f1d78 00000000 00000000 C c s e 0 48 0xa10f1d80 00000000 00000000 C c s e 0 49 0xa10f1d88 00000000 00000000 C c s e 0 50 0xa1channel 15 SDIO Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f1e00 00000000 00000000 C c s e 00 <- CURR<- PREV 1 0xa10f1e08 00000000 00000000 C c s e 00 2 0xa10f1e10 00000000 00000000 C c s e 00 3 0xa10f1e18 00000000 00000000 C c s e 00 4 0xa10f1e20 00000000 00000000 C c s e 00 5 0xa10f1e28 00000000 00000000 C c s e 00 6 0xa10f1e30 00000000 00000000 C c s e 00 7 0xa10f1e38 00000000 00000000 C c s e 00 8 0xa10f1e40 00000000 00000000 C c s e 00 9 0xa10f1e48 00000000 00000000 C c s e 00 10 0xa10f1e50 00000000 00000000 C c s e 00 11 0xa10f1e58 00000000 00000000 C c s e 00 12 0xa10f1e60 00000000 00000000 C c s e 00 13 0xa10f1e68 00000000 00000000 C c s e 00 14 0xa10f1e70 00000000 00000000 C c s e 00 15 0xa10f1e78 00000000 00000000 C c s e 00 16 0xa10f1e80 00000000 00000000 C c s e 00 17 0xa10f1e88 00000000 00000000 C c s e 00 18 0xa10f1e90 00000000 00000000 C c s e 00 19 0xa10f1e98 00000000 00000000 C c s e 00 20 0xa10f1ea0 00000000 00000000 C c s e 00 21 0xa10f1ea8 00000000 00000000 C c s e 00 22 0xa10f1eb0 00000000 00000000 C c s e 00 23 0xa10f1eb8 00000000 00000000 C c s e 00 24 0xa10f1ec0 00000000 00000000 C c s e 00 25 0xa10f1ec8 00000000 00000000 C c s e 00 26 0xa10f1ed0 00000000 00000000 C c s e 00 27 0xa10f1ed8 00000000 00000000 C c s e 00 28 0xa10f1ee0 00000000 00000000 C c s e 00 29 0xa10f1ee8 00000000 00000000 C c s e 00 30 0xa10f1ef0 00000000 00000000 C c s e 00 31 0xa10f1ef8 00000000 00000000 C c s e 00 32 0xa10f1f00 00000000 00000000 C c s e 00 33 0xa10f1f08 00000000 00000000 C c s e 00 34 0xa10f1f10 00000000 00000000 C c s e 00 35 0xa10f1f18 00000000 00000000 C c s e 00 36 0xa10f1f20 00000000 00000000 C c s e 00 37 0xa10f1f28 00000000 00000000 C c s e 00 38 0xa10f1f30 00000000 00000000 C c s e 00 39 0xa10f1f38 00000000 00000000 C c s e 00 40 0xa10f1f40 00000000 00000000 C c s e 00 41 0xa10f1f48 00000000 00000000 C c s e 00 42 0xa10f1f50 00000000 00000000 C c s e 00 43 0xa10f1f58 00000000 00000000 C c s e 00 44 0xa10f1f60 00000000 00000000 C c s e 00 45 0xa10f1f68 00000000 00000000 C c s e 00 46 0xa10f1f70 00000000 00000000 C c s e 00 47 0xa10f1f78 00000000 00000000 C c s e 00 48 0xa10f1f80 00000000 00000000 C c s e 00 49 0xa10f1f88 channel 16 MCTRL0 Rx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f2000 00000000 00000000 C c s e 0 <- CURR<- PREV 1 0xa10f2008 00000000 00000000 C c s e 0 2 0xa10f2010 00000000 00000000 C c s e 0 3 0xa10f2018 00000000 00000000 C c s e 0 4 0xa10f2020 00000000 00000000 C c s e 0 5 0xa10f2028 00000000 00000000 C c s e 0 6 0xa10f2030 00000000 00000000 C c s e 0 7 0xa10f2038 00000000 00000000 C c s e 0 8 0xa10f2040 00000000 00000000 C c s e 0 9 0xa10f2048 00000000 00000000 C c s e 0 10 0xa10f2050 00000000 00000000 C c s e 0 11 0xa10f2058 00000000 00000000 C c s e 0 12 0xa10f2060 00000000 00000000 C c s e 0 13 0xa10f2068 00000000 00000000 C c s e 0 14 0xa10f2070 00000000 00000000 C c s e 0 15 0xa10f2078 00000000 00000000 C c s e 0 16 0xa10f2080 00000000 00000000 C c s e 0 17 0xa10f2088 00000000 00000000 C c s e 0 18 0xa10f2090 00000000 00000000 C c s e 0 19 0xa10f2098 00000000 00000000 C c s e 0 20 0xa10f20a0 00000000 00000000 C c s e 0 21 0xa10f20a8 00000000 00000000 C c s e 0 22 0xa10f20b0 00000000 00000000 C c s e 0 23 0xa10f20b8 00000000 00000000 C c s e 0 24 0xa10f20c0 00000000 00000000 C c s e 0 25 0xa10f20c8 00000000 00000000 C c s e 0 26 0xa10f20d0 00000000 00000000 C c s e 0 27 0xa10f20d8 00000000 00000000 C c s e 0 28 0xa10f20e0 00000000 00000000 C c s e 0 29 0xa10f20e8 00000000 00000000 C c s e 0 30 0xa10f20f0 00000000 00000000 C c s e 0 31 0xa10f20f8 00000000 00000000 C c s e 0 32 0xa10f2100 00000000 00000000 C c s e 0 33 0xa10f2108 00000000 00000000 C c s e 0 34 0xa10f2110 00000000 00000000 C c s e 0 35 0xa10f2118 00000000 00000000 C c s e 0 36 0xa10f2120 00000000 00000000 C c s e 0 37 0xa10f2128 00000000 00000000 C c s e 0 38 0xa10f2130 00000000 00000000 C c s e 0 39 0xa10f2138 00000000 00000000 C c s e 0 40 0xa10f2140 00000000 00000000 C c s e 0 41 0xa10f2148 00000000 00000000 C c s e 0 42 0xa10f2150 00000000 00000000 C c s e 0 43 0xa10f2158 00000000 00000000 C c s e 0 44 0xa10f2160 00000000 00000000 C c s e 0 45 0xa10f2168 00000000 00000000 C c s e 0 46 0xa10f2170 00000000 00000000 C c s e 0 47 0xa10f2178 00000000 00000000 C c s e 0 48 0xa10f2180 00000000 00000000 C c s e 0 49 0xa10f2188 00000000 00000000 C c s e 0 50 0xchannel 17 MCTRL0 Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f2200 00000000 00000000 C c s e 00 <- CURR<- PREV 1 0xa10f2208 00000000 00000000 C c s e 00 2 0xa10f2210 00000000 00000000 C c s e 00 3 0xa10f2218 00000000 00000000 C c s e 00 4 0xa10f2220 00000000 00000000 C c s e 00 5 0xa10f2228 00000000 00000000 C c s e 00 6 0xa10f2230 00000000 00000000 C c s e 00 7 0xa10f2238 00000000 00000000 C c s e 00 8 0xa10f2240 00000000 00000000 C c s e 00 9 0xa10f2248 00000000 00000000 C c s e 00 10 0xa10f2250 00000000 00000000 C c s e 00 11 0xa10f2258 00000000 00000000 C c s e 00 12 0xa10f2260 00000000 00000000 C c s e 00 13 0xa10f2268 00000000 00000000 C c s e 00 14 0xa10f2270 00000000 00000000 C c s e 00 15 0xa10f2278 00000000 00000000 C c s e 00 16 0xa10f2280 00000000 00000000 C c s e 00 17 0xa10f2288 00000000 00000000 C c s e 00 18 0xa10f2290 00000000 00000000 C c s e 00 19 0xa10f2298 00000000 00000000 C c s e 00 20 0xa10f22a0 00000000 00000000 C c s e 00 21 0xa10f22a8 00000000 00000000 C c s e 00 22 0xa10f22b0 00000000 00000000 C c s e 00 23 0xa10f22b8 00000000 00000000 C c s e 00 24 0xa10f22c0 00000000 00000000 C c s e 00 25 0xa10f22c8 00000000 00000000 C c s e 00 26 0xa10f22d0 00000000 00000000 C c s e 00 27 0xa10f22d8 00000000 00000000 C c s e 00 28 0xa10f22e0 00000000 00000000 C c s e 00 29 0xa10f22e8 00000000 00000000 C c s e 00 30 0xa10f22f0 00000000 00000000 C c s e 00 31 0xa10f22f8 00000000 00000000 C c s e 00 32 0xa10f2300 00000000 00000000 C c s e 00 33 0xa10f2308 00000000 00000000 C c s e 00 34 0xa10f2310 00000000 00000000 C c s e 00 35 0xa10f2318 00000000 00000000 C c s e 00 36 0xa10f2320 00000000 00000000 C c s e 00 37 0xa10f2328 00000000 00000000 C c s e 00 38 0xa10f2330 00000000 00000000 C c s e 00 39 0xa10f2338 00000000 00000000 C c s e 00 40 0xa10f2340 00000000 00000000 C c s e 00 41 0xa10f2348 00000000 00000000 C c s e 00 42 0xa10f2350 00000000 00000000 C c s e 00 43 0xa10f2358 00000000 00000000 C c s e 00 44 0xa10f2360 00000000 00000000 C c s e 00 45 0xa10f2368 00000000 00000000 C c s e 00 46 0xa10f2370 00000000 00000000 C c s e 00 47 0xa10f2378 00000000 00000000 C c s e 00 48 0xa10f2380 00000000 00000000 C c s e 00 49 0xa10f2388channel 18 MCTRL1 Rx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f2400 00000000 00000000 C c s e 0 <- CURR<- PREV 1 0xa10f2408 00000000 00000000 C c s e 0 2 0xa10f2410 00000000 00000000 C c s e 0 3 0xa10f2418 00000000 00000000 C c s e 0 4 0xa10f2420 00000000 00000000 C c s e 0 5 0xa10f2428 00000000 00000000 C c s e 0 6 0xa10f2430 00000000 00000000 C c s e 0 7 0xa10f2438 00000000 00000000 C c s e 0 8 0xa10f2440 00000000 00000000 C c s e 0 9 0xa10f2448 00000000 00000000 C c s e 0 10 0xa10f2450 00000000 00000000 C c s e 0 11 0xa10f2458 00000000 00000000 C c s e 0 12 0xa10f2460 00000000 00000000 C c s e 0 13 0xa10f2468 00000000 00000000 C c s e 0 14 0xa10f2470 00000000 00000000 C c s e 0 15 0xa10f2478 00000000 00000000 C c s e 0 16 0xa10f2480 00000000 00000000 C c s e 0 17 0xa10f2488 00000000 00000000 C c s e 0 18 0xa10f2490 00000000 00000000 C c s e 0 19 0xa10f2498 00000000 00000000 C c s e 0 20 0xa10f24a0 00000000 00000000 C c s e 0 21 0xa10f24a8 00000000 00000000 C c s e 0 22 0xa10f24b0 00000000 00000000 C c s e 0 23 0xa10f24b8 00000000 00000000 C c s e 0 24 0xa10f24c0 00000000 00000000 C c s e 0 25 0xa10f24c8 00000000 00000000 C c s e 0 26 0xa10f24d0 00000000 00000000 C c s e 0 27 0xa10f24d8 00000000 00000000 C c s e 0 28 0xa10f24e0 00000000 00000000 C c s e 0 29 0xa10f24e8 00000000 00000000 C c s e 0 30 0xa10f24f0 00000000 00000000 C c s e 0 31 0xa10f24f8 00000000 00000000 C c s e 0 32 0xa10f2500 00000000 00000000 C c s e 0 33 0xa10f2508 00000000 00000000 C c s e 0 34 0xa10f2510 00000000 00000000 C c s e 0 35 0xa10f2518 00000000 00000000 C c s e 0 36 0xa10f2520 00000000 00000000 C c s e 0 37 0xa10f2528 00000000 00000000 C c s e 0 38 0xa10f2530 00000000 00000000 C c s e 0 39 0xa10f2538 00000000 00000000 C c s e 0 40 0xa10f2540 00000000 00000000 C c s e 0 41 0xa10f2548 00000000 00000000 C c s e 0 42 0xa10f2550 00000000 00000000 C c s e 0 43 0xa10f2558 00000000 00000000 C c s e 0 44 0xa10f2560 00000000 00000000 C c s e 0 45 0xa10f2568 00000000 00000000 C c s e 0 46 0xa10f2570 00000000 00000000 C c s e 0 47 0xa10f2578 00000000 00000000 C c s e 0 48 0xa10f2580 00000000 00000000 C c s e 0 49 0xa10f2588 00000000 00000000 C c s e 0 50 0xchannel 19 MCTRL1 Tx descriptor list: no address data pointer command bits (Own, Complete, SoP, EoP, Offset) --------------------------------------------------------------------------------- 0 0xa10f2600 00000000 00000000 C c s e 00 <- CURR<- PREV 1 0xa10f2608 00000000 00000000 C c s e 00 2 0xa10f2610 00000000 00000000 C c s e 00 3 0xa10f2618 00000000 00000000 C c s e 00 4 0xa10f2620 00000000 00000000 C c s e 00 5 0xa10f2628 00000000 00000000 C c s e 00 6 0xa10f2630 00000000 00000000 C c s e 00 7 0xa10f2638 00000000 00000000 C c s e 00 8 0xa10f2640 00000000 00000000 C c s e 00 9 0xa10f2648 00000000 00000000 C c s e 00 10 0xa10f2650 00000000 00000000 C c s e 00 11 0xa10f2658 00000000 00000000 C c s e 00 12 0xa10f2660 00000000 00000000 C c s e 00 13 0xa10f2668 00000000 00000000 C c s e 00 14 0xa10f2670 00000000 00000000 C c s e 00 15 0xa10f2678 00000000 00000000 C c s e 00 16 0xa10f2680 00000000 00000000 C c s e 00 17 0xa10f2688 00000000 00000000 C c s e 00 18 0xa10f2690 00000000 00000000 C c s e 00 19 0xa10f2698 00000000 00000000 C c s e 00 20 0xa10f26a0 00000000 00000000 C c s e 00 21 0xa10f26a8 00000000 00000000 C c s e 00 22 0xa10f26b0 00000000 00000000 C c s e 00 23 0xa10f26b8 00000000 00000000 C c s e 00 24 0xa10f26c0 00000000 00000000 C c s e 00 25 0xa10f26c8 00000000 00000000 C c s e 00 26 0xa10f26d0 00000000 00000000 C c s e 00 27 0xa10f26d8 00000000 00000000 C c s e 00 28 0xa10f26e0 00000000 00000000 C c s e 00 29 0xa10f26e8 00000000 00000000 C c s e 00 30 0xa10f26f0 00000000 00000000 C c s e 00 31 0xa10f26f8 00000000 00000000 C c s e 00 32 0xa10f2700 00000000 00000000 C c s e 00 33 0xa10f2708 00000000 00000000 C c s e 00 34 0xa10f2710 00000000 00000000 C c s e 00 35 0xa10f2718 00000000 00000000 C c s e 00 36 0xa10f2720 00000000 00000000 C c s e 00 37 0xa10f2728 00000000 00000000 C c s e 00 38 0xa10f2730 00000000 00000000 C c s e 00 39 0xa10f2738 00000000 00000000 C c s e 00 40 0xa10f2740 00000000 00000000 C c s e 00 41 0xa10f2748 00000000 00000000 C c s e 00 42 0xa10f2750 00000000 00000000 C c s e 00 43 0xa10f2758 00000000 00000000 C c s e 00 44 0xa10f2760 00000000 00000000 C c s e 00 45 0xa10f2768 00000000 00000000 C c s e 00 46 0xa10f2770 00000000 00000000 C c s e 00 47 0xa10f2778 00000000 00000000 C c s e 00 48 0xa10f2780 00000000 00000000 C c s e 00 49 0xa10f2788# # cat /proc/driver/ifx_dma/ifx_dma_chan_weight Qos dma channel weight list channel_num default_weight current_weight device Tx/Rx ------------------------------------------------------------ 0 00000064 00000064 PPE Rx 1 00000064 00000064 PPE Tx 2 00000064 00000064 PPE Tx 3 00000064 00000064 PPE Tx 4 00000064 00000064 PPE Tx 5 00000064 00000064 PPE Tx 6 00000064 00000048 PPE Rx 7 00000064 00000064 PPE Tx 8 00000064 00000064 DEU Rx 9 00000064 00000064 DEU Tx 10 00000064 00000064 DEU Rx 11 00000064 00000064 DEU Tx 12 00000064 00000064 SPI Rx 13 00000064 00000064 SPI Tx 14 00000064 00000064 SDIO Rx 15 00000064 00000064 SDIO Tx 16 00000064 00000064 MCTRL0 Rx 17 00000064 00000064 MCTRL0 Tx 18 00000064 00000064 MCTRL1 Rx 19 00000064 00000064 MCTRL1 Tx # cat /proc/partitions major minor #blocks name 31 0 64 mtdblock0 31 1 8128 mtdblock1 # cat /proc/mtd dev: size erasesize name mtd0: 00010000 00002000 "uboot" mtd1: 007f0000 00010000 "rootfs" # cat /proc/ifx_wdt IFX_WDT_PROC_READ IFX_WDT_CR(0xbf8803f0) : 0x00000000 IFX_WDT_SR(0xbf8803f8) : 0x00000000 # cat /usr/sbin/bringup_single_mii_1.sh #!/bin/sh ################################### # # Port0,1,2 as Lan with VID 25 and same grouping # Port4 as Wan with VID 5 # CPU is attached to Port6 in AR9 # ################################### brctl delif br0 eth0 ifconfig br0 down brctl delbr br0 vconfig add eth0 25 vconfig add eth0 5 ifconfig eth0 down #turn switch off mem -s 0x1e1080cc -w 0x000004e1 -u sleep 1 #set speed for port4,5,6 as 1000Mbit/s mem -s 0x1e1080cc -w 0x0bbb04f5 -u sleep 1 #enable port4,6 #mem -s 0x1e1080cc -w 0x00040481 -u #sleep 1 mem -s 0x1e1080cc -w 0x000404c1 -u sleep 1 #CPU is attached to port6 mem -s 0x1e1080cc -w 0x00c004e2 -u sleep 1 #grouping port0,1,2,6 and 4,6 individually mem -s 0x1e1080cc -w 0x04470403 -u sleep 1 mem -s 0x1e1080cc -w 0x04470423 -u sleep 1 mem -s 0x1e1080cc -w 0x04470443 -u sleep 1 mem -s 0x1e1080cc -w 0x04500483 -u sleep 1 mem -s 0x1e1080cc -w 0x043f04c3 -u sleep 1 #set vid for port0,1,2,4,6 mem -s 0x1e1080cc -w 0x00190404 -u sleep 1 mem -s 0x1e1080cc -w 0x00190424 -u sleep 1 mem -s 0x1e1080cc -w 0x00190444 -u sleep 1 mem -s 0x1e1080cc -w 0x00050484 -u sleep 1 mem -s 0x1e1080cc -w 0x10cc04c4 -u sleep 1 #turn switch on mem -s 0x1e1080cc -w 0x800004e1 -u sleep 1 ifconfig eth0 up ifconfig eth0.25 10.10.10.254 netmask 255.255.255.0 up ifconfig eth0.5 192.168.1.254 netmask 255.255.255.0 up sleep 1 echo wan lo 0 /proc/eth/genconf echo wan hi 10 /proc/eth/genconf ppacmd addlan -i eth0.25 ppacmd addwan -i eth0.5 ppacmd control --enable-lan --enable-wan # cat /usr/sbin/bringup_single_mii_2.sh #!/bin/sh ################################### # # Port0 as Lan with VID 25 # Port1 as Lan with VID 35 # Port2 as Lan with VID 45 # Port4 as Wan with VID 5 # CPU is attached to Port6 in AR9 # ################################### brctl delif br0 eth0 ifconfig br0 down brctl delbr br0 vconfig add eth0 25 vconfig add eth0 35 vconfig add eth0 45 vconfig add eth0 5 ifconfig eth0 down #turn switch off mem -s 0x1e1080cc -w 0x000004e1 -u sleep 1 #set speed for port4,5,6 as 1000Mbit/s mem -s 0x1e1080cc -w 0x0bbb04f5 -u sleep 1 #enable port4,6 #mem -s 0x1e1080cc -w 0x00040481 -u #sleep 1 mem -s 0x1e1080cc -w 0x000404c1 -u sleep 1 #CPU is attached to port6 mem -s 0x1e1080cc -w 0x00c004e2 -u sleep 1 #grouping port0,1,2,4,6 individually mem -s 0x1e1080cc -w 0x04410403 -u sleep 1 mem -s 0x1e1080cc -w 0x04420423 -u sleep 1 mem -s 0x1e1080cc -w 0x04440443 -u sleep 1 mem -s 0x1e1080cc -w 0x04500483 -u sleep 1 mem -s 0x1e1080cc -w 0x043f04c3 -u sleep 1 #set vid for port0,1,2,4,6 mem -s 0x1e1080cc -w 0x00190404 -u sleep 1 mem -s 0x1e1080cc -w 0x00230424 -u sleep 1 mem -s 0x1e1080cc -w 0x002d0444 -u sleep 1 mem -s 0x1e1080cc -w 0x00050484 -u sleep 1 mem -s 0x1e1080cc -w 0x10cc04c4 -u sleep 1 #turn switch on mem -s 0x1e1080cc -w 0x800004e1 -u sleep 1 ifconfig eth0 up ifconfig eth0.25 10.10.10.254 netmask 255.255.255.0 up ifconfig eth0.35 10.10.20.254 netmask 255.255.255.0 up ifconfig eth0.45 10.10.30.254 netmask 255.255.255.0 up ifconfig eth0.5 192.168.1.254 netmask 255.255.255.0 up sleep 1 echo wan lo 0 /proc/eth/genconf echo wan hi 10 /proc/eth/genconf ppacmd addlan -i eth0.25 ppacmd addlan -i eth0.35 ppacmd addlan -i eth0.45 ppacmd addwan -i eth0.5 ppacmd control --enable-lan --enable-wan


BootEnv

ROM VER: 1.1.3 CFG 01 DDR Access auto data-eye tuning Rev 0.1a DDR size from 0xa0000000 - 0xa1ffffff DDR check ok... start booting... U-Boot 1.1.5-LANTIQ-v-1.8.20 (Aug 19 2010 - 09:13:40) Boot from NOR flash AR9 BOARD CLOCK CPU 333M RAM 166M DRAM: 32 MB relocate_code start relocate_code finish. Flash: 8 MB In: serial Out: serial Err: serial Net: switch chip id=0000ffff amazon_s Switch Type "run flash_nfs" to mount root filesystem over NFS Hit any key to stop autoboot: 0 AMAZON_S # printenv bootcmd=run flash_flash bootdelay=3 baudrate=115200 serialnum="00E092000140" preboot=echo;echo Type "run flash_nfs" to mount root filesystem over NFS;echo bootfile=uImage mem=31M phym=32M ethaddr=00:E0:92:00:01:40 netdev=eth0 console=ttyS1 baudrate=115200 tftppath= loadaddr=0x80800000 rootpath=/mnt/full_fs rootfsmtd=/dev/mtdblock1 nfsargs= setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) ramargs=setenv bootargs root=/dev/ram rw addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):on addmisc=setenv bootargs $(bootargs) console=$(console),$(baudrate) ethaddr=$(ethaddr) phym=$(phym) mem=$(mem) panic=1 mtdparts=$(mtdparts) init=/etc/preinit quiet vpe1_load_addr=0x81f00000 vpe1_mem=1M ethwan=$(ethwan) flash_nfs=run nfsargs addip addmisc;bootm $(kernel_addr) net_nfs=tftp $(loadaddr) $(tftppath)$(bootfile);run nfsargs addip addmisc;bootm net_flash=tftp $(loadaddr) $(tftppath)$(bootfile); run flashargs addip addmisc; bootm net_ram=tftp $(loadaddr) $(tftppath)$(bootfile); run ramargs addip addmisc; bootm u-boot=u-boot.ifx rootfs=rootfs.img firmware=firmware.img fullimage=fullimage.img totalimage=totalimage.img load=tftp $(loadaddr) $(u-boot) update=protect off 1:0-2;era 1:0-2;cp.b $(loadaddr) B0000000 $(filesize) flashargs=setenv bootargs root=$(rootfsmtd) ro rootfstype=squashfs flash_flash=run flashargs addip addmisc; bootm $(kernel_addr) update_uboot=tftpboot $(loadaddr) $(tftppath)$(u-boot);erase all; cp.b $(loadaddr) b0000000 $(filesize); reset update_kernel=tftpboot $(loadaddr) $(tftppath)$(bootfile);upgrade $(loadaddr) $(filesize) update_rootfs=tftpboot $(loadaddr) $(tftppath)$(rootfs); upgrade $(loadaddr) $(filesize) update_firmware=tftpboot $(loadaddr) $(tftppath)$(firmware);upgrade $(loadaddr) $(filesize) update_fullimage=tftpboot $(loadaddr) $(tftppath)$(fullimage);upgrade $(loadaddr) $(filesize) update_totalimage=tftpboot $(loadaddr) $(tftppath)/$(totalimage);upgrade $(loadaddr) $(filesize) reset_ddr_config=prot off 0xB000FFE8 0xb000ffff; erase 0xB000FFE8 0xb000ffff 1 mtdparts=ifx_nor0:64k(uboot),-(rootfs) reset_uboot_config=prot off 0xB07FE000 0xB07FEFFF; erase 0xB07FE000 0xB07FEFFF 1 part0_begin=0xB0000000 part1_begin=0xB0010000 total_part=2 flash_end=0xB07FFFFF data_block0=uboot data_block1=rootfs data_block2=kernel data_block3=sysconfig data_block4=ubootconfig data_block5=fwdiag total_db=6 f_uboot_addr=0xB0000000 f_uboot_size=0 f_ubootconfig_addr=0xB07FE000 f_ubootconfig_size=0x1000 f_ubootconfig_end=0xB07FEFFF f_kernel_end=IFX_CFG_FLASH_KERNEL_IMAGE_END_ADDR f_firmware_addr=IFX_CFG_FLASH_FIRMWARE_IMAGE_START_ADDR f_firmware_size=IFX_CFG_FLASH_FIRMWARE_IMAGE_SIZE f_fwdiag_addr=0xB07FF000 f_fwdiag_size=0x400 f_ddrconfig_addr=0xB000FFE8 f_ddrconfig_size=24 ethact=amazon_s Switch bootargs=root=/dev/mtdblock1 ro rootfstype=squashfs ip=192.168.1.1:192.168.1.2::::eth0:on console=ttyS1,115200 ethaddr=00:E0:92:00:01:40 phym=32M mem=31M panic=1 mtdparts=ifx_nor0:64k(uboot),-(rootfs) init=/etc/preinit quiet vpe1_load_addr=0x81f00000 vpe1_mem=1M ethwan= filesize=511f88 fileaddr=80800000 ipaddr=192.168.1.1 serverip=192.168.1.2 f_rootfs_size=0x003f6a70 f_rootfs_addr=0xb0010000 f_rootfs_end=0xb0406a70 f_rootfs_crc=D1E97FE7 f_kernel_size=0x0011b490 f_kernel_addr=0xb06d2b70 kernel_addr=0xb06d2b70 f_kernel_crc=E217491B f_sysconfig_size=0x00001f77 f_sysconfig_addr=0xb07ee000 stdin=serial stdout=serial stderr=serial Environment size: 3440/4092 bytes AMAZON_S #


Bootlog

ROM VER: 1.1.3 CFG 01 DDR Access auto data-eye tuning Rev 0.1a DDR size from 0xa0000000 - 0xa1ffffff DDR check ok... start booting... U-Boot 1.1.5-LANTIQ-v-1.8.20 (Aug 19 2010 - 09:13:40) Boot from NOR flash AR9 BOARD CLOCK CPU 333M RAM 166M DRAM: 32 MB relocate_code start relocate_code finish. Flash: 8 MB In: serial Out: serial Err: serial Net: switch chip id=0000ffff amazon_s Switch Type "run flash_nfs" to mount root filesystem over NFS Hit any key to stop autoboot: 0 ## Booting image at b06d78f0 ... Image Name: MIPS IFXCPE Linux-2.6.20.19 Created: 2010-11-02 9:36:09 UTC Image Type: MIPS Linux Kernel Image (lzma compressed) Data Size: 1140432 Bytes = 1.1 MB Load Address: 80002000 Entry Point: 80349000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK No initrd ## Transferring control to Linux (at address 80349000) ... ## Giving linux memsize in MB, 32 Starting kernel ... Infineon xDSL CPE AR9 mips_hpt_frequency = 166666666, counter_resolution = 2 drivers/char/ifxmips_rcu.c:668:ifx_rcu_init: Can not register RCU device - -16 IFX CPE login: DAS 2434 BOOTLoader:1.1.5-LANTIQ-v-1.8.20 CPU:AR9-v Kernel:2.6.20.19 Software:UGW-4.2.1-832-1736-02Nov10 Tool Chain:3.4.6/0.9.29 The pid file is: /var/run/wscd.pid.ra0! gPassiveMsgQ Init success! gPassiveMsgID=0x4c3b5f41! gActiveMsgQ Init success! sock=5!(0x0x7ffd7128) Pthread(wscDevNLHandle)Now waiting for the netlink socket incoming message! Create netlink socket thread success! Create ioctl socket(6) success! . Error with UpnpInit -- -208 [: 1: unknown operand Bringup wan started for wan index 1 !! SIOCSIFADDR: No such device SIOCGIFFLAGS: No such device [: -lt: argument expected SIOCGIFFLAGS: No such device /usr/sbin/pppd: In file /etc/ppp/peers/pppoe1: unrecognized option 'eth1.3' cat: /tmp/adsl_status: No such file or directory Bringup wan started for wan index 2 !! SIOCSIFADDR: No such device SIOCGIFFLAGS: No such device udhcpc (v0.9.9-pre) started cat: /tmp/adsl_status: No such file or directory Sending discover... Sending discover... Sending discover... No lease, forking to background. IFX CPE login: admin Password: BusyBox v1.00 (2010.11.02-08:56+0000) Built-in shell (ash) Enter 'help' for a list of built-in commands. # uname -a Linux Aztech 2.6.20.19 #1 Tue Nov 2 17:31:28 SGT 2010 mips unknown


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toh/aztech/gr7000.txt · Last modified: 2018/06/02 22:31 by tmomas