arm_arm926ej-s

The ARM926EJ-S processor is a member of the ARM9 family of general-purpose microprocessors.
The ARM926EJ-S processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important.
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling you to trade off between high performance and high code density.
The ARM926EJ-S processor includes features for efficient execution of Java byte codes, providing Java performance similar to JIT, but without the associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug.
The ARM926EJ-S processor has a Harvard cached architecture and provides a complete high-performance processor subsystem, including:

• an ARM9EJ-S integer core
• a Memory Management Unit (MMU)
• separate instruction and data AMBA AHB bus interfaces
• separate instruction and data TCM interfaces.

The ARM926EJ-S processor provides support for external coprocessors enabling floating-point or other application-specific hardware acceleration to be added.
The ARM926EJ-S processor implements ARM architecture v5TEJ.
The ARM926EJ-S processor is a synthesizable macrocell. This means that you can optimize the macrocell for a particular target library, and that you can configure the memory system to suit your target application. You can individually configure the cache sizes to be any power of two between 4KB and 128KB. The tightly-coupled instruction and data memories are instantiated externally to the ARM926EJ-S macrocell, providing you with the flexibility of optimizing the memory subsystem for performance, power, and particular RAM type. The TCM interfaces enable nonzero wait state memory to be attached, in addition to providing a mechanism for supporting DMA.

source (technical reference manual)

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