• Highly configurable 32-bit processor core
  • Linux acceleration package including shared library address space identifier (ASID) support in MMU and load lock/store conditional instructions
  • MMU-based memory solution supports Linux and other high-end operating systems
  • Built-in DSP features include instruction and register extensions that accelerate signal processing algorithms
  • Optional DesignWare ARC XY Advanced DSP solution delivers the performance of dedicated DSP cores, allowing external logic and DSP blocks to be eliminated
  • DesignWare ARCompact™ 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets
  • JTAG debug port and optional embedded hardware breakpoints facilitate software debug
  • Delivered as synthesizable RTL source code (Verilog®), fully compatible with industry standard design methodologies and tool flows


This website uses cookies. By using the website, you agree with storing cookies on your computer. Also you acknowledge that you have read and understand our Privacy Policy. If you do not agree leave the website.More information about cookies
  • Last modified: 2024/02/12 11:43
  • by