arc_arc700

• Highly configurable 32-bit processor core
• Linux acceleration package including shared library address space identifier (ASID) support in MMU and load lock/store conditional instructions
• MMU-based memory solution supports Linux and other high-end operating systems
• Built-in DSP features include instruction and register extensions that accelerate signal processing algorithms
• Optional DesignWare ARC XY Advanced DSP solution delivers the performance of dedicated DSP cores, allowing external logic and DSP blocks to be eliminated
• DesignWare ARCompact™ 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets
• JTAG debug port and optional embedded hardware breakpoints facilitate software debug
• Delivered as synthesizable RTL source code (Verilog®), fully compatible with industry standard design methodologies and tool flows

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