StarFive RISC-V SoCs

RISC-V is a free, open, extensible instruction set architecture (ISA), the specification is now maintained by the nonprofit RISC-V Foundation.

StarFive produces a number of RISC-V SoCs, mostly based on the SiFive designs. Upstreaming the device / interface support for them is in progress.

• Port status: https://github.com/openwrt/openwrt/pull/13372
• Official doc site: https://doc-en.rvspace.org/index.html

CPU datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf

• → visionfive
• → beaglev

CPU datasheet: https://doc-en.rvspace.org/JH7110/PDF/JH7110_Datasheet.pdf

• → visionfive2