The CPU (Intellectual property core)

When looking at the usual Central processing unit a couple of things come into mind:

  1. Extensions to the Instruction Set, e.g. MMX or AVX or AES-NI)
  2. and its design manifesting into a concrete Microarchitecture (e.g. Core2 or NetBurst or AMD_K5)
  3. concrete CPUs designed conforming to the same microarchitecture further differentiate from one another in the Frequency and Cache sizes


  • x86 is one distinct ISA and the i386SX was one distinct microarchitecture, and the i486DX2 another one, and the Cyrix
  • ARMv5 is one distinct ISA and the ARM926EJ-S is one distinct microarchitecture based upon it
  • MIPS32 is one distinct ISA and the MIPS 24K, 34K or the 74K are all based upon it.

You could also look at the type of Processor:

When you want to purchase a CPU (or a couple of thousand) you have three choices:

To understand the difference between Hard IP and Soft IP you have to get a grasp of the processes of designing and of manufacturing of IC.

Without going into detail you could say, the ISA is the whole of commands (absolute instructions/machine code instruction) the programmer/compiler can see and use. If you program in assembler (or write machine code), you will have to know these instructions. If you program in a higher language, the compiler (or the cross-compiler) will take care of this for you. It will translate your source code into machine code for the ISA (in compiler surroundings abbreviated ARCH for architecture) specified.

When you “cross compile” it means that you compile the source code on a machine that has a different ISA than that of the target machine you will run the compiled code on. For this the compiler needs to know the ISA for your target ARCH (architecture). Follow this link to learn how to cross compile. For more information on ISA, see the white paper at: Instruction set.

Designing an Instruction Set is more just saying “I want to use these instructions”. The underlying logic of how data goes in/out and how it is manipulated when instructions are processed, this has to be designed as well. How all of this can be implemented in a physical Integrated Circuit (IC or simply Chip) has to be designed too. Some stages of this overall design are often covered by patents or other Intellectual Property protections. Some CPU design companies exist only to create and license their designs to others who will integrate them into their own physical devices.

Example: MIPS

You can find a distinct Wiki for GNU/Linux and the MIPS instruction set here:

MIPS (Microprocessor without Interlocked Pipeline Stages) is a instruction set architecture (ISA) developed by MIPS Computer Systems. Multiple revisions of the MIPS instruction set exist the only current ones being MIPS32 and MIPS64. As there are extensions to the x86 ISA, like MMX, SSE, 3DNow!, etc, there are some available for MIPS as well. MIPS Technologies calls them ASE (Application-specific extensions). Read about them here:


MIPS Classic Processors MIPS Aptiv Processors MIPS Warrior
4KSd M4K M14K 4KE M14Kc 24K 24KE 34K 74K 1004K 1074K microAptiv interAptiv proAptiv Warrior-M Warrior-I Warrior-P
  • AFAIK all MIPS classic processors are in-order execution CPUs because the developers claimed, that the silicon surface and power consumption of the OUT-OF-ORDER logic would outweigh the processing power benefit. Instead they experimented with Multi-Threading and such to achieve a similar processing power increase but with less silicon.
  • The newer MIPS Aptiv Processors are reported to be all Out-of-order CPUs.
  • Please do note, that there are a couple of MIPS32 and/or MIPS64 instruction set licensees, e.g. Broadcom, who design their own CPU Architectures based on the MIPS Instruction sets. Cf. companies for some overview.
  • Dunno about Linux support for this stuff here:

To understand the concrete differences between the different CPU designs, you will have to go This should only give you an overview to get a better grasp of the embedded world. And please understand, that 24KE is not necessarily a CPU you can buy, or even a CPU contained on the SoC. It the a plan to manufacture the IC of a CPU! A contractor can realize this 1:1 into IC but does not have to.

To understand a bit better, how this is embedded on the SoC, see

Example: ARM

The abbreviation stands for Advanced RISC Machine aka Acorn RISC Machine. ARM Holdings.

For some reasons, the companies does not want to compete with each other, so on the router/wifi market MIPS cores are predominant. On the smart phone market it is the other way around, and we have ARM exclusively. However there is at least one neat device on which OpenWrt is running, so we will include this:

ISA ISA+Extensions CPU Features Cache (I/D), MMU Devices Products
ARMv5ARMv5 TEJ ARM926EJ-S Thumb, Jazelle DBX, Enhanced DSP instructions variable, TCMs, MMU Texas Instruments OMAP1710, OMAP1610, OMAP1611, OMAP1612, OMAP-L137, OMAP-L138; Qualcomm MSM6100, MSM6125, MSM6225, MSM6245, MSM6250, MSM6255A, MSM6260, MSM6275, MSM6280, MSM6300, MSM6500, MSM6800; Freescale i.MX21, i.MX27, Atmel AT91SAM9, NXP Semiconductors, Samsung S3C2412 LPC30xx, NEC C10046F5-211-PN2-A SoC – undocumented core in the ATi Hollywood graphics chip used in the Wii,[25] Telechips TCC7801, TCC7901, ZiiLABS ZMS-05, Rockchip RK2806 and RK2808, NeoMagic MiMagic Family MM6, MM6+, MM8, MTV. Mobile phones: Sony Ericsson (K, W series); Siemens and Benq (x65 series and newer); LG Arena; , GPH Wiz, Squeezebox Duet Controller (Samsung S3C2412). Squeezebox Radio; Buffalo TeraStation Live (NAS); Drobo FS (NAS); Western Digital MyBook I World Edition; Western Digital MyBook II World Edition; Seagate FreeAgent DockStar STDSD10G-RK; Seagate FreeAgent GoFlex Home; Chumby Classic

To understand the concrete differences between the different versions, you will have to go somewhere else. This should only give you an overview to get a better grasp of the embedded world. And please understand, that ARM926EJ-S is not necessarily a CPU you can buy, or even a CPU contained on the SoC. It is only the model of a CPU! A contractor can realize this 1:1 into IC but does not have to. For example the manufacturer Marvell make the Marvell Feroceon CPU, which is based on the Design of the ARM926EJ-S (sometimes it includes CESA). Marvell Kirkwood is the denomination of a family of SoCs, not of a CPU design.

On, for example, there are some txt-documents about the ARM-architecture.

Example: Other


Code compiled for ARM should run on any ARM-ISA, but code speficifally compiled for ARMv7 will not run smoothly or not at all on an ARMv5 ISA. So, it is imperative to keep the ISA stable for many years, thus there are only few or no updates at all! To still be able to develop and advance the ISA, and thus give the programmer (or the compiler) more options to do theirs stuff, manufactures (or better developers) extend ISAs with so called extensions. See Template:Multimedia_extensions.

NOTE: In the FOSS-“World”, this isn't such a big issue, since we have the Source-Code and with an updated compiler we can recompile the code as we like and obtain binaries that work an any architecture. And actually we do exactly that at OpenWrt. When you choose the option toolchain you do download the very latest source code for the cross compiler and cross compile the source code with that!

While the ISA is only the set of commands available, to use it, you need to create a CPU based on one. While an abstraction of the ISA is build in silicon, the CPU needs more functional units to be able to work and also to perform as well as possible. The denomination for this is not clear-cut, everyone names differently. Instead of microarchitecture, sometimes this is referred to as “processor organization” or “processor design” or “processor implementation”. It deals with the organization of the different functional units of the CPU. For the same ISA, you could develop a whole lot of microarchitectures. A hopefully good example is the intel i486 and the intel Pentium Pro (it's the immediate predecessor the Pentium II, whereas the Pentium is not). Both CPU have (almost) the same ISA, but very different MAs.

IP core means “Intellectual Property Core”. It is a piece of software that can be licensed from companies such as MIPS or ARM. It's a chip layout design and consists of schematics and descriptions to manufacture ICs with the functionality of a CPU. With this, the licensee can go to a semiconductor foundry and commission the manufacturing of Chips with the functionality of merely the CPU purchased. But usually, the designs of the CPU are combined with the designs of other ICs serving other tasks. Then the licensee commissions the manufacture of Chips, which do have the functionality of a complete soc, and not merely that of a CPU.

Often different types can be licensed, a soft IP core or hard IP core. To understand the difference between them you need to understand even more of the chip design process. Maybe the article ic helps a little with that.

Also, exceptionally there is a good article about this in the wikipedia: IP core.

SoC What do licensees include in a SoC?


A Manufacturer of “devices”/routers/access points buys SoCs, RAM-Chips, Flash-Chips, etc. from the manufacturers of these and solder them onto a circuit board. Then they put the whole thing into a body housing, write documentation for the end customer and sell them whole sale.

For a List of Devices and Manufacturers, simply have look at the Table of Hardware.

Integrated Circuit whether CPU, GPU, DRAM, SRAM, DPS, FPU etc. all are realized as ICs.

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  • Last modified: 2021/10/15 09:06
  • by bobafetthotmail