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toh:zyxel:xgs1250-12 [2022/02/24 13:28] – [Supported Versions] Template info text can go. borrominitoh:zyxel:xgs1250-12 [2022/11/28 15:48] – [Tags] added torev
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 ====== ZyXEL XGS1250-12 ====== ====== ZyXEL XGS1250-12 ======
  
-The ZyXEL XGS1250-12 is a web managed 11 + 1-port Multi-Gigabit L3 switch. It has 8 Gigabit ports, three 2.5/5/10GBit Ethernet ports and one SFP+ 10GBit uplink cage+<WRAP center round important 50%> 
 +\\ Support for the RTL930x subtarget is still very fresh. SFP+ does not work yet. 
 +</WRAP> 
 + 
 +The ZyXEL XGS1250-12 is a web managed 11 + 1-port Multi-Gigabit L3 switch. Connectivity: 
 +  * **8** Gigabit ports 
 +  * **3** 1000/2500/5000/10000BaseT Ethernet ports 
 +  * **1** SFP+ 10GBit uplink cage
  
 {{media:zyxel:xgs1250-12:zyxel_xgs1250-12.png?500|Frontal view}} {{media:zyxel:xgs1250-12:zyxel_xgs1250-12.png?500|Frontal view}}
- 
-<WRAP BOX> 
-FIXME 
-===== Getting started with a new Device Page ===== 
-  - This is an empty template that suggests the information that should be present on a well-constructed Device Page. This means, that **you have to fill it with life and information.** 
-  - There are several "fixme" tags with text on a light background (like this text) throughout this template. As you fill in the page, remove those tags so that people can judge its completeness. 
-  - When there are no more "fixme" tags left, delete this one too, along with the ''<nowiki><WRAP></nowiki>'' that encloses it. 
- 
-===== Keep the articles modular ===== 
-  * Please include only model specific information, omit bla,bla and put everything generic into separate articles 
-  * If you have no time to write certain stuff, link to [[docs:start]] 
-  * [[docs:guide-user:base-system:start]] should lead the way, do not explain this again 
-  * DO NOT provide a complete howto here! Instead //groom// the [[docs:start|general documentation]]. 
-</WRAP> 
  
 ===== Supported Versions ===== ===== Supported Versions =====
Line 86: Line 79:
  
 ==== Flash Layout ==== ==== Flash Layout ====
-<WRAP BOX> +The XGS1250-12 has a 16 MiB Macronix MX25L12833F NOR flash chipThe realtek target uses a dynamic kernel/rootfs splitso actual sizes of the ''kernel''''rootfs'' and ''rootfs_data'' partitions may vary.
-FIXME //[[:docs:techref:flash.layout#discovery_how_to_find_out|Find out flash layout]]then add the flash layout table here (copypaste, modify the [[docs:techref:flash.layout#partitioning_of_the_flash|example]]).//+
  
-Please check out the article [[docs:techref:flash.layout|Flash layout]]. It contains examples and explanations that describe how to document the flash layout. +^   XGS1250-12  Flash Layout (OpenWrt)     ^^^^^^^^^^ 
-</WRAP>+^ Layer0  |  raw NOR flash memory chip ([[wp>Serial Peripheral Interface Bus|spi]]0.0: mx25l12805d) 16384 KiB  ||||||||| 
 +^ Layer1  |  mtd0 **//u-boot//** 896 KiB  |  mtd1 **//u-boot-env//** 64 KiB  |  mtd2 **//u-boot-env2//** 64 KiB  |  mtd3 **//jffs//** 1024 KiB  |  mtd4 **//jffs2//** 1024 KiB  |  mtd5  **//runtime//** 13184 KiB  |||  mtd9 **//log//** 128 KiB | 
 +^ Layer2  | |||||  mtd6 **//kernel//** 2752 KiB  |  mtd7 **//rootfs//** 10432 KiB  ||   | 
 +^ <color magenta>mountpoint</color>  |  ||||||  <color magenta>''/''</color>  ||      | 
 +^ filesystem    ||||||  [[docs:techref:filesystems#overlayfs|OverlayFS]]  ||       | 
 +^ Layer3        ||||||  |  mtd8 **//rootfs_data//** 7232 KiB  |      | 
 +^ Size in KiB  |  896 KiB  |  64 KiB  |  64 KiB  |  1024 KiB  |  1024 KiB  |  2752 KiB  |  3200 KiB  |  7232 KiB  |  128 KiB  | 
 +^ Name          **//u-boot//**  |  **//u-boot-env//**  |  **//u-boot-env2//**  |  **//jffs//**  |  **//jffs2//**  |  **//kernel//**  |  |  **//rootfs_data//**  |  | 
 +^ <color magenta>mountpoint</color  |  //none//  |  //none//  |  //none//  |  //none//  |  //none//  |  //none//    <color magenta>''/rom''</color>  |  <color magenta>''/overlay''</color>    //none// 
 +^ filesystem    //none//  |  //none//  |  //none//  |  //none//  |  //none//  |  //none//  |  [[docs:techref:filesystems#SquashFS]]  |  [[docs:techref:filesystems#JFFS2]]  |  //none//  |
  
 ==== OEM easy installation ==== ==== OEM easy installation ====
  
-<WRAP BOX> +  * Connect serial as per the [[toh:zyxel:xgs1250-12#serial|layout]]. 
-FIXME //The instructions below are for Broadcom devices and only serve as an example.//\\ +  * Navigate to 'Management' in the OEM web interface and click on 'Firmware upgrade' to the left
-**//Remove modify them if they do not apply to this particular device!//**+  Upload the OpenWrt initramfs image, and wait till the switch reboots into OpenWrt. 
 +  Connect to the device through serial and change the U-boot boot command: <code># fw_setenv bootcmd 'rtk network on; boota'</code> 
 +  * Reboot, scp the sysupgrade image to /tmp, verify the checksum and flash it: <code># sysupgrade /tmp/openwrt-realtek-rtl930x-zyxel_xgs1250-12-squashfs-sysupgrade.bin</code> 
 +  Upon reboot, you have a functional OpenWrt installation. Leave the bootcmd value as is - without ''rtk network on'' the switch will fail to initialise the network. 
 +==== Booting OpenWrt from RAM ====
  
-This section deals with +->  [[docs:guide-user:installation:generic.flashing.tftp]]
-  * How you install OpenWrt from a device freshly opened +
-  * The steps required such as reset to factory defaults if the device has already been configured+
  
-**Note:** Reset router to factory defaults if it has been previously configured. +The XGS1250-12 can boot from the network, but for that you'd need to manipulate the boot commandZyXEL password protected the U-boot environment. However, if you change the bootcmd to a bogus value from within OpenWrt, you'll get dropped to a shell and be able to tftp load a ramdisk image. The instructions below assume a functional TFTP server. This is an 'invasive' procedure in the sense that you //will// need to install OpenWrt once to change the bootcmdOnce that's done you can reinstall the OEM firmware if you'd like. Keep in mind <color #ed1c24>**you will need serial access for every single boot**</coloras long as your bootcmd is bogus. Once you switch back to the default ''boota'' command, the switch will boot through, but you will not be able to access U-boot anymore until you change the bootcmd again. This is excellent for testing purposes, but unsuited for production use.
-  * Browse to ''<nowiki>http://192.168.1.1/Upgrade.asp</nowiki>'' +
-  * Upload .bin file to router +
-  * Wait for it to reboot +
-  * Telnet to 192.168.1.1 and set a root password, or browse to ''<nowiki>http://192.168.1.1</nowiki>'' if LuCI is installed. +
-</WRAP>+
  
-==== OEM installation using the TFTP method ==== 
  
-->  [[docs:guide-user:installation:generic.flashing.tftp]] 
  
-=== Specific values needed for tftp ===+=== Specific values needed for TFTP ===
  
-<WRAP BOX>+^ Bootloader TFTP server IPv4 address  | 192.168.1.111   | 
 +^ Firmware TFTP image                  | [[:downloads|Latest OpenWrt release]] (**''NOTE:''** Name must contain //"initramfs"//) |
  
-FIXME Enter values for "FILL-IN" below+=== Instructions ===
  
-^ Bootloader tftp server IPv4 address  | FILL-IN   +  * Connect serial as per the [[toh:zyxel:xgs#serial|serial settings]]
-^ Bootloader MAC address (special)     | FILL-IN   | +  Navigate to 'Managementin the OEM web interface and click on 'Firmware upgradeto the left. 
-^ Firmware tftp image                  | [[:downloads|Latest OpenWrt release]] (**''NOTE:''** Name must contain //"tftp"//) | +  Upload the OpenWrt initramfs image, and wait till the switch reboots. 
-^ TFTP transfer window                 | FILL-IN seconds                                | +  Connect to the device through serial and change the boot command to a bogus command, so U-boot will drop you to a shell next time you boot: <code># fw_setenv bootcmd 'rtk network on; bootu'</code> 
-^ TFTP window start                    | approximately FILL-IN seconds after power on   | +  * Reboot 
-^ TFTP client required IP address      | FILL-IN                                        | +  * Load the ramdisk in the U-boot shell: <code># tftpboot 0x84f00000 10.0.0.10:openwrt-realtek-rtl930x-zyxel_xgs1250-12-initramfs-kernel.bin</code>
- +
-</WRAP>+
  
 ===== Upgrading OpenWrt ===== ===== Upgrading OpenWrt =====
Line 188: Line 183:
  
 <WRAP BOX> <WRAP BOX>
-FIXME Please fill in real values for this device, then remove the EXAMPLEs 
  
 ==== Network interfaces ==== ==== Network interfaces ====
 The default network configuration is: The default network configuration is:
 ^ Interface Name   ^ Description                  ^ Default configuration    ^ ^ Interface Name   ^ Description                  ^ Default configuration    ^
-| br-lan           EXAMPLE LAN & WiFi           EXAMPLE 192.168.1.1/24   +| br-lan           | LAN            | 192.168.1.1/24   |
-| vlan0 (eth0.0)   | EXAMPLE LAN ports (1 to 4)   | EXAMPLE None             | +
-| vlan1 (eth0.1)   | EXAMPLE WAN port             | EXAMPLE DHCP             | +
-| wl0              | EXAMPLE WiFi                 | EXAMPLE Disabled         |+
  
 </WRAP> </WRAP>
Line 246: Line 237:
 filter  : Brand=ZyXEL filter  : Brand=ZyXEL
 filter  : Model=XGS1250-12 filter  : Model=XGS1250-12
-filter  : Versions= 
 ---- ----
  
Line 279: Line 269:
 -> [[docs:techref:hardware:port.serial]] general information about the serial port, serial port cable, etc. -> [[docs:techref:hardware:port.serial]] general information about the serial port, serial port cable, etc.
  
-How to connect to the Serial Port of this specific device:\\ +Serial is pretty straightforward on this switch. There's an angled UART serial connector to the right side, sitting vertically in between the ventilation slits. The serial header can be connected to from the outside with a standard 2.54mm header. Pins are, from top to bottom
-**Insert photo of PCB with markings for serial port**+  Vcc (3.3V) 
 +  TX 
 +  RX 
 +  GND
  
-<WRAP BOX> +Layout is exactly the same as for the ZyXEL GS1900-10HP (casing color being black):
-FIXME //Replace EXAMPLE by real values.// +
-</WRAP>+
  
-^ Serial connection parameters\\ for ZyXEL XGS1250-12 @@Version@@ EXAMPLE 115200, 8N1 |+{{:media:zyxel:xgs1250-12:zyxel_xgs1250-12_uart.jpg?direct&400|}} 
 + 
 +^ Serial connection parameters for ZyXEL XGS1250-12 | 115200, 8N1 |
  
 ==== JTAG ==== ==== JTAG ====
Line 309: Line 302:
  
 ==== OpenWrt bootlog ==== ==== OpenWrt bootlog ====
-<WRAP bootlog> +<WRAP bootlog><nowiki> 
-<nowiki>COPY HERE THE BOOTLOG ONCE OPENWRT IS INSTALLED AND RUNNING</nowiki> +U-Boot Version V1.0.0.2 (Aug 11 2020 - 14:10:19)
-</WRAP>\\+
  
-===== Notes ===== +Board: RTL9300 CPU:800MHz LX:175MHz DDR:600MHz 
-//Space for additional notes, links to forum threads or other resources.//+DRAM:  128 MB 
 +SPI-F: MXIC/C22018/MMIO16-1/ModeC 1x16 MB (plr_flash_info @ 83f747e4) 
 +Loading 65536B env. variables from offset 0xe0000 
 +Net:   Net Initialization Skipped 
 +No ethernet found. 
 + 0  
 +## Booting kernel from Legacy Image at 81000000 ... 
 +   Image Name:   MIPS OpenWrt Linux-5.10.92 
 +   Created:      2022-01-31  12:58:24 UTC 
 +   Image Type:   MIPS Linux Kernel Image (gzip compressed) 
 +   Data Size:    6632884 Bytes = 6.3 MB 
 +   Load Address: 80000000 
 +   Entry Point:  80000400 
 +   Verifying Checksum ... OK 
 +   Uncompressing Kernel Image ... OK
  
-  * ...+Starting kernel ...
  
 +[    0.000000] Linux version 5.10.92 (1800x@crunchbot) (mips-openwrt-linux-musl-gcc (OpenWrt GCC 11.2.0 r18681+56-5d110c0161) 11.2.0, GNU ld (GNU Binutils) 2.37) #0 Mon Jan 31 12:58:24 2022
 +[    0.000000] RTL838X model is 0
 +[    0.000000] RTL839X model is 0
 +[    0.000000] RTL93XX model is 93021001
 +[    0.000000] SoC Type: RTL9302B
 +[    0.000000] Kernel command line: 
 +[    0.000000] printk: bootconsole [early0] enabled
 +[    0.000000] CPU0 revision is: 00019555 (MIPS 34Kc)
 +[    0.000000] MIPS: machine is Zyxel XGS1250-12 Switch
 +[    0.000000] Initrd not found or empty - disabling initrd
 +[    0.000000] Using appended Device Tree.
 +[    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
 +[    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
 +[    0.000000] Zone ranges:
 +[    0.000000]   Normal   [mem 0x0000000000000000-0x0000000007ffffff]
 +[    0.000000] Movable zone start for each node
 +[    0.000000] Early memory node ranges
 +[    0.000000]   node   0: [mem 0x0000000000000000-0x0000000007ffffff]
 +[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
 +[    0.000000] On node 0 totalpages: 32768
 +[    0.000000]   Normal zone: 288 pages used for memmap
 +[    0.000000]   Normal zone: 0 pages reserved
 +[    0.000000]   Normal zone: 32768 pages, LIFO batch:7
 +[    0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
 +[    0.000000] pcpu-alloc: [0] 0 
 +[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32480
 +[    0.000000] Kernel command line: console=ttyS0,115200
 +[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
 +[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
 +[    0.000000] Writing ErrCtl register=0000000c
 +[    0.000000] Readback ErrCtl register=0000000c
 +[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
 +[    0.000000] Memory: 113356K/131072K available (5146K kernel code, 616K rwdata, 492K rodata, 9928K init, 203K bss, 17716K reserved, 0K cma-reserved)
 +[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
 +[    0.000000] NR_IRQS: 256
 +[    0.000000] random: get_random_bytes called from 0x8061eabc with crng_init=0
 +[    0.000000] CPU frequency from device tree: 800MHz
 +[    0.000000] rtl9300_clockevent_init called for cpu0
 +[    0.000000] rtl9300_clockevent_init using IRQ 8
 +[    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 4778151116 ns
 +[    0.000010] sched_clock: 32 bits at 400MHz, resolution 2ns, wraps every 5368709118ns
 +[    0.008488] Calibrating delay loop... 531.66 BogoMIPS (lpj=2658304)
 +[    0.067031] pid_max: default: 32768 minimum: 301
 +[    0.072219] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
 +[    0.080082] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
 +[    0.090634] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build
 +[    0.101357] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
 +[    0.112038] futex hash table entries: 256 (order: -1, 3072 bytes, linear)
 +[    0.119455] pinctrl core: initialized pinctrl subsystem
 +[    0.125513] NET: Registered protocol family 16
 +[    0.178077] clocksource: Switched to clocksource MIPS
 +[    0.184660] NET: Registered protocol family 2
 +[    0.189534] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear)
 +[    0.197921] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
 +[    0.207062] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear)
 +[    0.215365] TCP bind hash table entries: 1024 (order: 0, 4096 bytes, linear)
 +[    0.223006] TCP: Hash tables configured (established 1024 bind 1024)
 +[    0.230044] UDP hash table entries: 256 (order: 0, 4096 bytes, linear)
 +[    0.237089] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes, linear)
 +[    0.244969] NET: Registered protocol family 1
 +[    0.471604] workingset: timestamp_bits=14 max_order=15 bucket_order=1
 +[    0.482789] squashfs: version 4.0 (2009/01/31) Phillip Lougher
 +[    0.489137] jffs2: version 2.2 (NAND) (SUMMARY) (ZLIB) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
 +[    0.502014] realtek_gpio_probe probing RTL GPIO
 +[    0.544029] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
 +[    0.552022] printk: console [ttyS0] disabled
 +[    0.556658] 18002000.uart: ttyS0 at MMIO 0x18002000 (irq = 30, base_baud = 10937500) is a 16550A
 +[    0.566238] printk: console [ttyS0] enabled
 +[    0.566238] printk: console [ttyS0] enabled
 +[    0.575472] printk: bootconsole [early0] disabled
 +[    0.575472] printk: bootconsole [early0] disabled
 +[    0.805647] brd: module loaded
 +[    0.812615] spi-nor spi0.0: mx25l12805d (16384 Kbytes)
 +[    0.818484] 6 fixed-partitions partitions found on MTD device spi0.0
 +[    0.825550] Creating 6 MTD partitions on "spi0.0":
 +[    0.830934] 0x000000000000-0x0000000e0000 : "u-boot"
 +[    0.838662] 0x0000000e0000-0x0000000f0000 : "u-boot-env"
 +[    0.845512] 0x0000000f0000-0x000000100000 : "u-boot-env2"
 +[    0.854305] 0x000000100000-0x000000200000 : "jffs"
 +[    0.860632] 0x000000200000-0x000000300000 : "jffs2"
 +[    0.868846] 0x000000300000-0x000001000000 : "firmware"
 +[    0.885215] libphy: Fixed MDIO Bus: probed
 +[    0.892068] Probing RTL838X eth device pdev: 82075800, dev: 82075810
 +[    0.918641] Found SoC ID: 9302: RTL9302B, family 9300
 +[    0.924284] Using MAC 000000e04c000000
 +[    0.928574] set sds port 24 to 6
 +[    0.932160] set sds port 25 to 7
 +[    0.935740] set sds port 26 to 8
 +[    0.939371] set sds port 27 to 9
 +[    0.943010] rtl838x_mdio_init Looking at port 0
 +[    0.948038] rtl838x_mdio_init phy mode of port 0 is qsgmii
 +[    0.954170] rtl838x_mdio_init Looking at port 1
 +[    0.959260] rtl838x_mdio_init phy mode of port 1 is qsgmii
 +[    0.965361] rtl838x_mdio_init Looking at port 2
 +[    0.970433] rtl838x_mdio_init phy mode of port 2 is qsgmii
 +[    0.976526] rtl838x_mdio_init Looking at port 3
 +[    0.981596] rtl838x_mdio_init phy mode of port 3 is qsgmii
 +[    0.987690] rtl838x_mdio_init Looking at port 4
 +[    0.992759] rtl838x_mdio_init phy mode of port 4 is qsgmii
 +[    0.998896] rtl838x_mdio_init Looking at port 5
 +[    1.003929] rtl838x_mdio_init phy mode of port 5 is qsgmii
 +[    1.010059] rtl838x_mdio_init Looking at port 6
 +[    1.015093] rtl838x_mdio_init phy mode of port 6 is qsgmii
 +[    1.021222] rtl838x_mdio_init Looking at port 7
 +[    1.026258] rtl838x_mdio_init phy mode of port 7 is qsgmii
 +[    1.032388] rtl838x_mdio_init Looking at port 24
 +[    1.037520] rtl838x_mdio_init phy mode of port 24 is usxgmii
 +[    1.043842] rtl838x_mdio_init Looking at port 25
 +[    1.049013] rtl838x_mdio_init phy mode of port 25 is usxgmii
 +[    1.055300] rtl838x_mdio_init Looking at port 26
 +[    1.060468] rtl838x_mdio_init phy mode of port 26 is usxgmii
 +[    1.066755] rtl838x_mdio_init Looking at port 27
 +[    1.071931] rtl838x_mdio_init phy mode of port 27 is 10gbase-r
 +[    1.078453] rtl838x_mdio_init Looking at port 28
 +[    1.083581] rtl838x_mdio_init phy mode of port 28 is internal
 +[    1.090701] c45_mask: 000e0000
 +[    1.094109] libphy: rtl930x-eth-mdio: probed
 +[    1.526126] REALTEK RTL9300 SERDES mdio-bus:1b: Detected internal RTL9300 Serdes
 +[    1.534432] rtl9300_configure_serdes: Port 27, SerDes is 9
 +[    1.544574] rtl9300_configure_serdes CMU BAND is 16
 +[    1.550039] rtl9300_sds_rst 31
 +[    1.573415] rtl9300_configure_serdes PATCHING SerDes 9
 +[    1.580195] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
 +[    1.586194] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
 +[    1.593996] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
 +[    1.600125] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
 +[    1.607799] rtl9300_phy_enable_10g_1g set medium: 00000000
 +[    1.613923] rtl9300_phy_enable_10g_1g set medium after: 00000002
 +[    1.640618] rtl9300_configure_serdes: Configuring RTL9300 SERDES 9, mode 1a
 +[    1.650387] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
 +[    1.660447] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
 +[    1.688378] rtl9300_force_sds_mode --------------------- serdes 9 forcing to 0 ...
 +[    1.696795] rtl9300_force_sds_mode: SDS: 9, mode 0
 +[    1.702163] rtl9300_force_sds_mode: SDS mode 1f
 +[    1.710231] rtl9300_force_sds_mode --------------------- serdes 9 forcing to 0 ...
 +[    1.718687] rtl9300_force_sds_mode: SDS: 9, mode 25
 +[    1.724108] rtl9300_force_sds_mode: SDS mode 1a
 +[    2.548072] random: fast init done
 +[    6.443249] rtl9300_force_sds_mode --------------------- serdes 9 forced to 1a DONE
 +[    6.451796] start_1.1.1 initial value for sds 9
 +[    6.484843] end_1.1.1 --
 +[    6.487658] start_1.1.2 Load DFE init. value
 +[    6.493429] end_1.1.2
 +[    6.495950] start_1.1.3 disable LEQ training,enable DFE clock
 +[    6.508370] end_1.1.3 --
 +[    6.511179] start_1.1.4 offset cali setting
 +[    6.516818] end_1.1.4
 +[    6.519368] start_1.1.5 LEQ and DFE setting
 +[    6.531031] end_1.1.5
 +[    6.540567] start_1.2.1 ForegroundOffsetCal_Manual
 +[    6.547889] end_1.2.1
 +[    6.555904] start_1.2.3 Foreground Calibration
 +[    6.569418] rtl9300_do_rx_calibration_2_3: fgcal_gray: 20, fgcal_binary 20
 +[    6.578097] rtl9300_do_rx_calibration_2_3: end_1.2.3
 +[    6.583617] start_1.4.1
 +[    6.805235] end_1.4.1
 +[    6.807952] start_1.4.2
 +[    6.816494] vth_set_bin = 4
 +[    6.819250] vth_set_bin = 2
 +[    6.823352] Vth Maunal = 1
 +[    6.935280] Tap0 Sign : +
 +[    6.938330] tap0_coef_bin = 20
 +[    6.942239] tap0 manual = 1
 +[    6.948649] end_1.4.2
 +[    6.951757] start_1.5.2
 +[    7.028187] end_1.5.2
 +[    7.115709] i2c /dev entries driver
 +[    7.122354] rtl9300_i2c_probe probing I2C adapter
 +[    7.127614] i2c-rtl9300 1b00036c.i2c-rtl9300: SCL speed 100000, mode is 0
 +[    7.135221] rtl9300_i2c_probe scl_num 0
 +[    7.139522] rtl9300_i2c_probe sda_num 1
 +[    7.145623] NET: Registered protocol family 10
 +[    7.159285] Segment Routing with IPv6
 +[    7.163466] NET: Registered protocol family 17
 +[    7.168868] 8021q: 802.1Q VLAN Support v1.8
 +[    7.174308] libphy: SFP SMBus: probed
 +[    7.178610] sfp sfp-p12: Host maximum power 1.0W
 +[    7.516087] libphy: rtl838x slave mii: probed
 +[    7.521088] rtl83xx_mdio_probe found port 0
 +[    7.525747] rtl83xx_mdio_probe found port 1
 +[    7.530441] rtl83xx_mdio_probe found port 2
 +[    7.535089] rtl83xx_mdio_probe found port 3
 +[    7.539773] rtl83xx_mdio_probe found port 4
 +[    7.544420] rtl83xx_mdio_probe found port 5
 +[    7.549103] rtl83xx_mdio_probe found port 6
 +[    7.553750] rtl83xx_mdio_probe found port 7
 +[    7.558446] rtl83xx_mdio_probe found port 24
 +[    7.563194] rtl83xx_mdio_probe found port 25
 +[    7.567933] rtl83xx_mdio_probe found port 26
 +[    7.572719] rtl83xx_mdio_probe found port 27
 +[    7.577466] rtl83xx_mdio_probe found port 28
 +[    7.595997] rtl93xx_setup called
 +[    7.599683] In rtl83xx_vlan_setup
 +[    7.603363] In rtl930x_vlan_profile_setup
 +[    7.607813] In rtl930x_vlan_profile_setup
 +[    7.612315] UNKNOWN_MC_PMASK: 000000001fffffff
 +[    7.617255] VLAN 0: L2 learn: 0; Unknown MC PMasks: L2 1fffffff, IPv4 1fffffff, IPv6: 1fffffff
 +[    7.617262]   Routing enabled: IPv4 UC y, IPv6 UC y, IPv4 MC y, IPv6 MC y
 +[    7.634429]   Bridge enabled: IPv4 MC n, IPv6 MC n,
 +[    7.639891] VLAN profile 0: raw 00033000 00000000 1fffffff 1fffffff 1fffffff
 +[    8.718087] rtl83xx_enable_phy_polling:          f0000ff
 +[    8.723997] rtl930x_pie_init
 +[    8.728271] rtl83xx-switch switch@1b000000 lan1 (uninitialized): PHY [mdio-bus:01] driver [REALTEK RTL8218D] (irq=POLL)
 +[    8.742078] rtl83xx-switch switch@1b000000 lan2 (uninitialized): PHY [mdio-bus:02] driver [REALTEK RTL8218D] (irq=POLL)
 +[    8.755837] rtl83xx-switch switch@1b000000 lan3 (uninitialized): PHY [mdio-bus:03] driver [REALTEK RTL8218D] (irq=POLL)
 +[    8.769543] rtl83xx-switch switch@1b000000 lan4 (uninitialized): PHY [mdio-bus:04] driver [REALTEK RTL8218D] (irq=POLL)
 +[    8.783353] rtl83xx-switch switch@1b000000 lan5 (uninitialized): PHY [mdio-bus:05] driver [REALTEK RTL8218D] (irq=POLL)
 +[    8.797163] rtl83xx-switch switch@1b000000 lan6 (uninitialized): PHY [mdio-bus:06] driver [REALTEK RTL8218D] (irq=POLL)
 +[    8.810973] rtl83xx-switch switch@1b000000 lan7 (uninitialized): PHY [mdio-bus:07] driver [REALTEK RTL8218D] (irq=POLL)
 +[    8.824793] rtl83xx-switch switch@1b000000 lan8 (uninitialized): PHY [mdio-bus:08] driver [REALTEK RTL8218D] (irq=POLL)
 +[    8.840035] Aquantia AQR113C mdio-bus:18: FW 5.4, Build 10, Provisioning 1
 +[    8.849761] rtl83xx-switch switch@1b000000 lan9 (uninitialized): PHY [mdio-bus:18] driver [Aquantia AQR113C] (irq=POLL)
 +[    8.865016] Aquantia AQR113C mdio-bus:19: FW 5.4, Build 10, Provisioning 1
 +[    8.874742] rtl83xx-switch switch@1b000000 lan10 (uninitialized): PHY [mdio-bus:19] driver [Aquantia AQR113C] (irq=POLL)
 +[    8.889999] Aquantia AQR113C mdio-bus:1a: FW 5.4, Build 10, Provisioning 1
 +[    8.899776] rtl83xx-switch switch@1b000000 lan11 (uninitialized): PHY [mdio-bus:1a] driver [Aquantia AQR113C] (irq=POLL)
 +[    8.913951] rtl83xx-switch switch@1b000000: configuring for fixed/internal link mode
 +[    8.922649] rtl93xx_phylink_mac_config port 28, mode 1, phy-mode: internal, speed 10000, link 0
 +[    8.932693] DSA: tree 0 setup
 +[    8.936036] LINK state irq: 23
 +[    8.939522] In rtl83xx_setup_qos
 +[    8.943162] L3_IPUC_ROUTE_CTRL 00002000, IPMC_ROUTE 00000500, IP6UC_ROUTE 00014580, IP6MC_ROUTE 00012880
 +[    8.953740] L3_IPUC_ROUTE_CTRL 00002001, IPMC_ROUTE 00000501, IP6UC_ROUTE 00014581, IP6MC_ROUTE 00012881
 +[    8.964314] L3_IP_ROUTE_CTRL 00000130
 +[    8.968507] rtl930x_dbgfs_init called
 +[    9.025314] Freeing unused kernel memory: 9928K
 +[    9.030419] This architecture does not have kernel memory protection.
 +[    9.037587] Run /init as init process
 +[    9.041686]   with arguments:
 +[    9.044982]     /init
 +[    9.047492]   with environment:
 +[    9.051004]     HOME=/
 +[    9.053618]     TERM=linux
 +[    9.056798] rtl93xx_phylink_mac_config port 28, mode 1, phy-mode: internal, speed 10000, link 1
 +[    9.066550] rtl83xx-switch switch@1b000000: Link is Up - 10Gbps/Full - flow control off
 +[    9.075508] rtl83xx_fib_event_work_do: FIB4 default rule failed
 +[    9.787289] init: Console is alive
 +[    9.791653] init: - watchdog -
 +[    9.808811] kmodloader: loading kernel modules from /etc/modules-boot.d/*
 +[    9.819555] kmodloader: done loading kernel modules from /etc/modules-boot.d/*
 +[    9.838290] init: - preinit -
 +[   10.061493] random: jshn: uninitialized urandom read (4 bytes read)
 +[   10.153740] random: jshn: uninitialized urandom read (4 bytes read)
 +[   10.735413] random: jshn: uninitialized urandom read (4 bytes read)
 +[   10.945581] RESETTING 9300, CPU_PORT 28
 +[   11.150240] rtl838x-eth 1b00a300.ethernet eth0: configuring for fixed/internal link mode
 +[   11.159250] In rtl838x_mac_config, mode 1
 +[   11.165143] rtl83xx-switch switch@1b000000 lan1: configuring for phy/qsgmii link mode
 +[   11.173943] rtl93xx_phylink_mac_config port 0, mode 0, phy-mode: qsgmii, speed -1, link 0
 +[   11.183072] rtl93xx_phylink_mac_config SDS is 0
 +[   11.188143] rtl93xx_phylink_mac_config: unknown serdes mode: qsgmii
 +[   11.195571] 8021q: adding VLAN 0 to HW filter on device lan1
 +[   11.202223] In rtl838x_mac_config, mode 1
 +[   11.206702] rtl838x-eth 1b00a300.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
 +[   11.222073] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
 +[   11.229165] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   11.236599] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   11.253203] rtl83xx_fib_event_work_do: FIB4 failed
 +[   11.267119] rtl83xx_fib_event_work_do: FIB4 failed
 +[   11.278040] rtl83xx_fib_event_work_do: FIB4 failed
 +[   11.287511] rtl83xx_fib_event_work_do: FIB4 failed
 +Press the [f] key and hit [enter] to enter failsafe mode
 +Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level
 +[   13.281422] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   15.407785] rtl83xx_fib4_del: no such gateway: 0.0.0.0
 +[   15.418182] rtl83xx_fib4_del: no such gateway: 0.0.0.0
 +[   15.423914] rtl83xx_fib4_del: no such gateway: 0.0.0.0
 +[   15.445602] procd: - early -
 +[   15.448951] rtl83xx_fib4_del: no such gateway: 0.0.0.0
 +[   15.455037] procd: - watchdog -
 +[   16.823826] procd: - watchdog -
 +[   16.827875] procd: - ubus -
 +[   16.839656] urandom_read: 2 callbacks suppressed
 +[   16.839665] random: ubusd: uninitialized urandom read (4 bytes read)
 +[   16.881175] random: ubusd: uninitialized urandom read (4 bytes read)
 +[   16.888836] random: ubusd: uninitialized urandom read (4 bytes read)
 +[   16.898595] procd: - init -
 +Please press Enter to activate this console.
 +[   17.489255] kmodloader: loading kernel modules from /etc/modules.d/*
 +[   17.585617] xt_time: kernel timezone is -0000
 +[   17.627514] kmodloader: done loading kernel modules from /etc/modules.d/*
 +[   17.832236] urngd: v1.0.2 started.
 +[   18.025336] random: crng init done
 +[   18.029202] random: 2 urandom warning(s) missed due to ratelimiting
 +[   22.325328] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   45.576659] in rtl838x_eth_stop
 +[   45.580292] rtl838x-eth 1b00a300.ethernet eth0: Link is Down
 +[   46.097384] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   46.104857] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   46.112312] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   46.119762] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   46.881014] Using MAC 0000bccf4fe81aae
 +[   46.885351] RESETTING 9300, CPU_PORT 28
 +[   47.090001] rtl838x-eth 1b00a300.ethernet eth0: configuring for fixed/internal link mode
 +[   47.098993] In rtl838x_mac_config, mode 1
 +[   47.103714] In rtl838x_mac_config, mode 1
 +[   47.108265] rtl838x-eth 1b00a300.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
 +[   47.135359] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
 +[   47.142479] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   47.149986] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   47.371447] rtl83xx-switch switch@1b000000 lan1: configuring for phy/qsgmii link mode
 +[   47.380246] rtl93xx_phylink_mac_config port 0, mode 0, phy-mode: qsgmii, speed -1, link 0
 +[   47.389390] rtl93xx_phylink_mac_config SDS is 0
 +[   47.394427] rtl93xx_phylink_mac_config: unknown serdes mode: qsgmii
 +[   47.401759] 8021q: adding VLAN 0 to HW filter on device lan1
 +[   47.450796] switch: port 1(lan1) entered blocking state
 +[   47.456624] switch: port 1(lan1) entered disabled state
 +[   47.462975] device lan1 entered promiscuous mode
 +[   47.468186] device eth0 entered promiscuous mode
 +[   47.531862] rtl930x_set_l3_egress_intf writing to index 0: 00000201 10101492
 +[   47.568207] rtl83xx_fib_event_work_do: FIB4 default rule failed
 +[   47.574802] Not offloading default route for now
 +[   47.598970] rtl83xx-switch switch@1b000000 lan2: configuring for phy/qsgmii link mode
 +[   47.607696] rtl93xx_phylink_mac_config port 1, mode 0, phy-mode: qsgmii, speed -1, link 0
 +[   47.616862] rtl93xx_phylink_mac_config SDS is 0
 +[   47.621948] rtl93xx_phylink_mac_config: unknown serdes mode: qsgmii
 +[   47.629498] 8021q: adding VLAN 0 to HW filter on device lan2
 +[   47.810012] switch: port 2(lan2) entered blocking state
 +[   47.815834] switch: port 2(lan2) entered disabled state
 +[   47.822078] device lan2 entered promiscuous mode
 +[   47.910528] rtl83xx-switch switch@1b000000 lan3: configuring for phy/qsgmii link mode
 +[   47.919329] rtl93xx_phylink_mac_config port 2, mode 0, phy-mode: qsgmii, speed -1, link 0
 +[   47.928474] rtl93xx_phylink_mac_config SDS is 0
 +[   47.933511] rtl93xx_phylink_mac_config: unknown serdes mode: qsgmii
 +[   47.940975] 8021q: adding VLAN 0 to HW filter on device lan3
 +[   48.077261] switch: port 3(lan3) entered blocking state
 +[   48.083150] switch: port 3(lan3) entered disabled state
 +[   48.148770] device lan3 entered promiscuous mode
 +[   48.186432] rtl83xx-switch switch@1b000000 lan4: configuring for phy/qsgmii link mode
 +[   48.195231] rtl93xx_phylink_mac_config port 3, mode 0, phy-mode: qsgmii, speed -1, link 0
 +[   48.204386] rtl93xx_phylink_mac_config SDS is 0
 +[   48.209466] rtl93xx_phylink_mac_config: unknown serdes mode: qsgmii
 +[   48.216808] 8021q: adding VLAN 0 to HW filter on device lan4
 +[   48.278655] switch: port 4(lan4) entered blocking state
 +[   48.284481] switch: port 4(lan4) entered disabled state
 +[   48.301673] device lan4 entered promiscuous mode
 +[   48.338474] rtl83xx-switch switch@1b000000 lan5: configuring for phy/qsgmii link mode
 +[   48.347197] rtl93xx_phylink_mac_config port 4, mode 0, phy-mode: qsgmii, speed -1, link 0
 +[   48.356360] rtl93xx_phylink_mac_config SDS is 0
 +[   48.361439] rtl93xx_phylink_mac_config: unknown serdes mode: qsgmii
 +[   48.369083] 8021q: adding VLAN 0 to HW filter on device lan5
 +[   48.418667] switch: port 5(lan5) entered blocking state
 +[   48.424493] switch: port 5(lan5) entered disabled state
 +[   48.442687] device lan5 entered promiscuous mode
 +[   48.498467] rtl83xx-switch switch@1b000000 lan6: configuring for phy/qsgmii link mode
 +[   48.507196] rtl93xx_phylink_mac_config port 5, mode 0, phy-mode: qsgmii, speed -1, link 0
 +[   48.516359] rtl93xx_phylink_mac_config SDS is 0
 +[   48.521438] rtl93xx_phylink_mac_config: unknown serdes mode: qsgmii
 +[   48.529126] 8021q: adding VLAN 0 to HW filter on device lan6
 +[   48.610536] switch: port 6(lan6) entered blocking state
 +[   48.616363] switch: port 6(lan6) entered disabled state
 +[   48.649321] device lan6 entered promiscuous mode
 +[   48.690748] rtl83xx-switch switch@1b000000 lan7: configuring for phy/qsgmii link mode
 +[   48.699547] rtl93xx_phylink_mac_config port 6, mode 0, phy-mode: qsgmii, speed -1, link 0
 +[   48.708692] rtl93xx_phylink_mac_config SDS is 0
 +[   48.713728] rtl93xx_phylink_mac_config: unknown serdes mode: qsgmii
 +[   48.721101] 8021q: adding VLAN 0 to HW filter on device lan7
 +[   48.839986] switch: port 7(lan7) entered blocking state
 +[   48.845805] switch: port 7(lan7) entered disabled state
 +[   48.852070] device lan7 entered promiscuous mode
 +[   48.894349] rtl83xx-switch switch@1b000000 lan8: configuring for phy/qsgmii link mode
 +[   48.903142] rtl93xx_phylink_mac_config port 7, mode 0, phy-mode: qsgmii, speed -1, link 0
 +[   48.912287] rtl93xx_phylink_mac_config SDS is 0
 +[   48.917323] rtl93xx_phylink_mac_config: unknown serdes mode: qsgmii
 +[   48.925095] 8021q: adding VLAN 0 to HW filter on device lan8
 +[   48.985614] switch: port 8(lan8) entered blocking state
 +[   48.991508] switch: port 8(lan8) entered disabled state
 +[   48.997687] device lan8 entered promiscuous mode
 +[   49.038201] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   49.045633] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   49.063841] rtl83xx_fib_event: FIB_RULE ADD/DELL for IPv6 not supported
 +[   49.094711] rtl83xx_fib_event_work_do: FIB4 default rule failed
 +
 +
 +
 +BusyBox v1.35.0 (2022-01-31 12:30:10 UTC) built-in shell (ash)
 +
 +  _______                     ________        __
 +       |.-----.-----.-----.|  |  |  |.----.|  |_
 +     ||  _  |  -__|     ||  |  |  ||   _||   _|
 + |_______||   __|_____|__|__||________||__|  |____|
 +          |__| W I R E L E S S   F R E E D O M
 + -----------------------------------------------------
 + OpenWrt SNAPSHOT, r18681+57-5d110c0161
 + -----------------------------------------------------
 + Hardware: Zyxel XGS1250-12 Switch
 +
 +=== WARNING! =====================================
 +There is no root password defined on this device!
 +Use the "passwd" command to set up a new password
 +in order to prevent unauthorized SSH logins.
 +--------------------------------------------------
 +root@OpenWrt:/
 +</nowiki>
 +</WRAP>\\
 +
 +===== Notes =====
 +  * SFP+ cage does not work yet on OpenWrt.
 +  * The network needs to be initialised by the bootloader through the ''rtk network on'' command. Otherwise the network won't work.
 ===== Tags ===== ===== Tags =====
 [[meta:tags|How to add tags]] [[meta:tags|How to add tags]]
  
-{{tag>Aquantia Realtek 16flash 128ram GigabitEthernet 10Gbit SFP_plus}}+{{tag>Aquantia Realtek 16flash 128ram GigabitEthernet 10Gbit SFP_plus 1button serial U-boot 12v_powered}}
  • Last modified: 2024/12/10 16:41
  • by hmartin