TP-Link RE200

The TP-Link RE200 is a wall-pluggable dual-band wireless range extender (802.11b/g/n and 802.11a/n/ac) based on the MediaTek SoCs with an Ethernet port. The RE200v1 is based on a MT7620A SoC, while the RE200v3 is based on a MT7628A SoC. The information below is for RE200v1!

The RE200v1 is currently being worked on and a pull request has been created at https://github.com/openwrt/openwrt/pull/2632.

Serial port: TTL voltage, 57600 bps, 8N1.

Interrupting U-Boot depends on your terminal: for interrupting U-Boot, you must not send a line feed!

Installation is only possible via Serial. You need to configure a TFTP server at 192.168.0.10 and put the -factory.bin image as “test.bin”. Then, interrupt the boot loader by pressing '2', accept the defaults and OpenWrt will be installed to flash.

Download an OEM firmware from TP-Link and prepare it as follows (we need to strip the first 0x200 bytes TP-Link header and the next 0x20000 bytes U-Boot):

dd if=re200v1_eu_3_14_2_up_boot\(160329\).bin of=re200v1_tftp.bin bs=1 skip=131584

Put the resulting re200v1_tftp.bin image as “test.bin” to your TFTP server. Install it as you would install OpenWrt.

U-Boot 1.1.3 (Aug 19 2014 - 17:43:44)

Board: Ralink APSoC DRAM:  64 MB
relocate_code Pointer at: 83fb4000
enable ephy clock...done. rf reg 29 = 5
SSC disabled.
spi_wait_nsec: 29
spi device id: 1c 30 17 1c 30 (30171c30)
find flash: EN25Q64
============================================
Ralink UBoot Version: 4.1.0.0
This UBoot has been rewritten by TPLINK *_*
--------------------------------------------
ASIC 7620_MP (Port5<->None)
DRAM component: 512 Mbits DDR, width 16
DRAM bus: 16 bit
Total memory: 64 MBytes
Flash component: SPI Flash
Date:Aug 19 2014  Time:17:43:44
============================================
icache: sets:512, ways:4, linesz:32 ,total:65536
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 580 MHZ ####
 estimate memory size =64 Mbytes

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   6: Load ART data then write to Flash via TFTP.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.

You choosed 4
                                                                              0
raspi_read: from:20028 len:6


4: System Enter Boot Command Line Interface.

U-Boot 1.1.3 (Aug 19 2014 - 17:43:44)
MT7620 # ?
?       - alias for 'help'
bootm   - boot application image from memory
cp      - memory copy(add cp.b by HouXB)
erase   - erase SPI FLASH memory
go      - start application at address 'addr'
help    - print online help
loadb   - load binary file over serial line (kermit mode)
md      - memory display
mdio   - Ralink PHY register R/W command !!
mm      - memory modify (auto-incrementing)
nm      - memory modify (constant address)
printenv- print environment variables
reset   - Perform RESET of the CPU
rf      - read/write rf register
saveenv - save environment variables to persistent storage
setenv  - set environment variables
tftpboot- boot image via network using TFTP protocol
version - print monitor version
MT7620 # printenv
bootcmd=tftp
bootdelay=1
baudrate=57600
ethaddr="00:AA:BB:CC:DD:10"
ipaddr=192.168.0.254
serverip=192.168.0.10
stdin=serial
stdout=serial
stderr=serial

Environment size: 152/4092 bytes
MT7620 #

Photos of v1.X PCB:

How to add tags