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toh:snr:cpe-me2-lite [2024/12/11 14:24] – [Installation] wertwert4pdatoh:snr:cpe-me2-lite [2024/12/18 15:02] (current) – [Info] frollic
Line 103: Line 103:
  
 <WRAP BOX> <WRAP BOX>
-FIXME //The instructions below are for Broadcom devices and only serve as an example.//\\ 
-**//Remove / modify them if they do not apply to this particular device!//** 
- 
 This section deals with This section deals with
   * How you install OpenWrt from a device freshly opened   * How you install OpenWrt from a device freshly opened
Line 111: Line 108:
  
 **Note:** Reset router to factory defaults if it has been previously configured. **Note:** Reset router to factory defaults if it has been previously configured.
-  Browse to ''<nowiki>http://192.168.1.1/Upgrade.asp</nowiki>'' + 
-  * Upload .bin file to router +**Flash instruction via WEB (old factory firmware 1.10.x)*
-  Wait for it to reboot +    1. Boot SNR-CPE-ME2-Lite normally with "Router" mode 
-  Telnet to 192.168.1.1 and set a root password, or browse to ''<nowiki>http://192.168.1.1</nowiki>'' if LuCI is installed.+    2. Access to "http://192.168.1.1/" and open "Administration -Management" page 
 +    3Select the OpenWrt sysupgrade image in "Firmware update" section and click "Update" button 
 +    4. Wait ~120 seconds to complete flashing 
 + 
 +**Note: For new factory firmware (EasyWRT 2.6.x) need downgrade to old factory image firstIt possible from web interface.**  
 +   
 </WRAP> </WRAP>
  
Line 207: Line 209:
 ===== Hardware ===== ===== Hardware =====
 ==== Info ==== ==== Info ====
-<WRAP BOX> +==== Info ====
-FIXME +
-  - This table is automatically generated, **once the correct filters for Brand and Model are set.** +
-  - If you see "Nothing." instead of a table, please **edit this section and adjust the filters with the proper Brand and Model.** Just try, it's easy. +
-  - If you still don't see a table here, or a table filled with '¿': [[toh:start|Is there already a Techdata page available]] for SNR CPE-ME2-Lite ? If not: [[meta:create_new_dataentry_page|Create one]]. +
-  - If you see a table with the desired device data, everything is OK and you can delete this text and the ''<nowiki><WRAP></nowiki>'' that encloses it. +
-  - If it still doesn't work: Don't panic, calm down, take a deep breath and [[:contact|contact a wiki admin]] (tmomas) for help. +
-</WRAP>+
  
----- datatemplatelist dttpllist ---- 
-template: meta:template_datatemplatelist 
-cols    : Brand, Model, Versions, Device Type, Availability, Supported Since Commit_git, Supported since Rel, Supported current Rel, Unsupported, Bootloader, CPU, Target, CPU MHz, Flash MBs, RAM MB, Switch, Ethernet 100M ports_, Ethernet Gbit ports_, Comments network ports_, Modem, VLAN, WLAN 2.4GHz, WLAN 5.0GHz, WLAN Hardwares, WLAN Comments_, Detachable Antennas_, USB ports_, SATA ports_, Comments USB SATA ports_, Serial, JTAG, LED count, Button count, Power supply, Device Techdata_pageid, Forum topic URL_url, wikidevi URL_url, OEM Device Homepage URL_url, Firmware OEM Stock URL_url, Firmware OpenWrt Install URL_url, Firmware OpenWrt Upgrade URL_url, Comments_ 
-filter  : Brand=SNR 
-filter  : Model=CPE-ME2-Lite 
-filter  : Versions=rev.B 
----- 
  
 +<!-- ToH: {
 +  "source": "json",
 +  "dom": "t",
 +  "paging": false,
 +  "rotate": true,
 +  "shownColumns": ["brand", "model", "version", "devicetype", "availability", "supportedsincecommit", "supportedsincerel", "supportedcurrentrel", "unsupported_functions", "bootloader", "cpu", "target", "cpumhz", "flashmb", "rammb", "switch", "ethernet100mports", "ethernet1gports", "commentsnetworkports", "modem", "vlan", "wlan24ghz", "wlan50ghz", "wlanhardware", "wlancomments", "detachableantennas", "usbports", "sataports", "commentsusbsataports", "serial", "jtag", "ledcount", "buttoncount", "powersupply", "deviceid", "owrt_forum_topic_url", "wikideviurl", "oemdevicehomepageurl", "firmwareoemstockurl", "firmwareopenwrtinstallurl", "firmwareopenwrtupgradeurl", "comments"],
 +  "filterColumns": {"brand": "^SNR$", "model": "^CPE-ME2-SFP$"}
 +} -->
 ==== Photos ==== ==== Photos ====
 /* =====>>>>> Standard size for photos: add ?400 to the medialink                                */ /* =====>>>>> Standard size for photos: add ?400 to the medialink                                */
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 <WRAP BOX> <WRAP BOX>
   * To remove the cover and open the device:   * To remove the cover and open the device:
-  - Ordered List Item Unscrew the 4 Phillips screws from the bottom of the device.+  - Unscrew the 4 Phillips screws from the bottom of the device.
   - There are 6 latches around the perimeter between the halves of the case. They need to be pressed by inserting a plastic card or other flat object between the halves.   - There are 6 latches around the perimeter between the halves of the case. They need to be pressed by inserting a plastic card or other flat object between the halves.
 </WRAP> </WRAP>
Line 284: Line 280:
 ===== Bootlogs ===== ===== Bootlogs =====
 ==== OEM bootlog ==== ==== OEM bootlog ====
 +fw version - SNR-CPE-ME2-Lite-1.10.9.1708231534.bin:
 +<WRAP bootlog>
 +<nowiki>
 +===================================================================
 +                MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC)
 +                CPU=500000000 HZ BUS=166666666 HZ
 +==================================================================
 +Change MPLL source from XTAL to CR...
 +do MEMPLL setting..
 +MEMPLL Config : 0x11100000
 +3PLL mode + External loopback
 +=== XTAL-40Mhz === DDR-1200Mhz ===
 +PLL2 FB_DL: 0xf, 1/0 = 556/468 3D000000
 +PLL3 FB_DL: 0xf, 1/0 = 650/374 3D000000
 +PLL4 FB_DL: 0x16, 1/0 = 548/476 59000000
 +do DDR setting..[01F40000]
 +Apply DDR3 Setting...(use customer AC)
 +          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120
 +      --------------------------------------------------------------------------------
 +0000:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0001:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0002:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0003:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0004:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0005:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0006:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0007:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0008:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0009:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +000A:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +000B:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +000C:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +000D:   0    0    0    0    0    0    0    0    0    0    0    0    1    1    1    1
 +000E:   0    0    0    0    0    0    1    1    1    1    1    1    1    1    1    1
 +000F:   0    1    1    1    1    1    1    1    1    1    1    1    0    0    0    0
 +0010:   1    1    1    1    1    1    0    0    0    0    0    0    0    0    0    0
 +0011:   1    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0012:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0013:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0014:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0015:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0016:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0017:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0018:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +0019:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +001A:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +001B:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +001C:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +001D:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +001E:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +001F:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 +DRAMC_DQSCTL1[0e0]=13000000
 +DRAMC_DQSGCTL[124]=80000033
 +rank 0 coarse = 15
 +rank 0 fine = 48
 +B:|    0    0    0    0    0    0    0    0    0    0    1    1    1    0    0    0
 +opt_dle value:11
 +DRAMC_DDR2CTL[07c]=C287223D
 +DRAMC_PADCTL4[0e4]=000022B3
 +DRAMC_DQIDLY1[210]=0F0F0C0F
 +DRAMC_DQIDLY2[214]=0D0F0E0F
 +DRAMC_DQIDLY3[218]=0C0E090C
 +DRAMC_DQIDLY4[21c]=0C0C0E0B
 +DRAMC_R0DELDLY[018]=00002020
 +==================================================================
 +                RX      DQS perbit delay software calibration
 +==================================================================
 +1.0-15 bit dq delay value
 +==================================================================
 +bit|      1  2  3  4  5  6  7  8  9
 +--------------------------------------
 +0 |    14 11 14 13 12 11 15 13 11 9
 +10 |    12 11 9 12 10 9
 +--------------------------------------
 +
 +==================================================================
 +2.dqs window
 +x=pass dqs delay value (min~max)center
 +y=0-7bit DQ of every group
 +input delay:DQS0 =32 DQS1 = 32
 +==================================================================
 +bit     DQS0     bit      DQS1
 +0  (1~60)30  8  (2~60)31
 +1  (1~61)31  9  (2~62)32
 +2  (1~59)30  10  (1~60)30
 +3  (1~60)30  11  (1~62)31
 +4  (0~59)29  12  (1~60)30
 +5  (0~59)29  13  (1~60)30
 +6  (1~59)30  14  (1~60)30
 +7  (3~62)32  15  (1~57)29
 +==================================================================
 +3.dq delay value last
 +==================================================================
 +bit|    0  1  2  3  4  5  6  7  8   9
 +--------------------------------------
 +0 |    15 12 15 15 15 14 15 13 12 9
 +10 |    14 12 11 14 12 12
 +==================================================================
 +==================================================================
 +     TX  perbyte calibration
 +==================================================================
 +DQS loop = 15, cmp_err_1 = ffff0000
 +dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1
 +dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2
 +DQ loop=15, cmp_err_1 = ffff0000
 +dqs_perbyte_dly.last_dqdly_pass[0]=15,  finish count=1
 +dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=2
 +byte:0, (DQS,DQ)=(8,8)
 +byte:1, (DQS,DQ)=(8,8)
 +DRAMC_DQODLY1[200]=88888888
 +DRAMC_DQODLY2[204]=88888888
 +20,data:88
 +[EMI] DRAMC calibration passed
 +
 +===================================================================
 +                MT7621   stage1 code done
 +                CPU=500000000 HZ BUS=166666666 HZ
 +===================================================================
 +
 +
 +U-Boot 1.1.3 (Jun 25 2020 - 13:46:13)
 +
 +Board: MediaTek APSoC DRAM: 128 MB
 +
 +Config XHCI 40M PLL
 +******************************
 +Software System Reset Occurred
 +******************************
 +MediaTek SPI flash driver, SPI clock: 31MHz
 +spi device id: 1c 70 18 1c
 +find flash: EN25QH128A
 +*** Warning - bad CRC, using default environment
 +
 +============================================
 +MediaTek U-Boot Version: 5.0.1.0-6
 +--------------------------------------------
 +ASIC MT7621A DualCore (MAC to MT7530 Mode)
 +DRAM_CONF_FROM: Auto-Detection
 +DRAM_TYPE: DDR3
 +DRAM bus: 16 bit
 +Xtal Mode=3 OCP Ratio=1/3
 +Flash component: SPI Flash
 +Date:Jun 25 2020  Time:13:46:13
 +============================================
 +icache: sets:256, ways:4, linesz:32, total:32768
 +dcache: sets:256, ways:4, linesz:32, total:32768
 +
 + #### The CPU freq = 880 MHZ ####
 + estimate memory size = 128 Mbytes
 +
 + Reset MT7530
 +set LAN/WAN WLLLL
 +
 +Please choose the operation:
 +   0: Load system code then write to Flash via Serial.
 +   1: Load system code to SDRAM via TFTP.
 +   2: Load system code then write to Flash via TFTP.
 +   3: Boot system code via Flash (default).
 +   4: Enter boot command line interface.
 +   7: Load U-Boot code then write to Flash via Serial.
 +   9: Load U-Boot code then write to Flash via TFTP.                                                                                      0
 +
 +
 +3: System Boot system code via Flash.
 +## Checking image at bc050000 ...
 +   Image Name:   SNR-CPE-ME2-Lite
 +   Image Type:   MIPS Linux Kernel Image (lzma compressed)
 +   Data Size:    12040042 Bytes = 11.5 MB
 +   Load Address: 81001000
 +   Entry Point:  812e0300
 +   Verifying Checksum ... OK
 +   Uncompressing Kernel Image ... OK
 +No initrd
 +## Transferring control to Linux (at address 812e0300) ...
 +## Giving linux memsize in MB, 128
 +
 +Starting kernel ...
 +
 +6
 +LINUX started...
 +DetectRAMsequence
 +MAX memory:[469762048]
 +RAM size detected:[134217728]
 +FullviewRAM:[134217728]
 +Linux version 3.4.113.185 (sfstudio_at_mail.ru@wive-ng.sf.net) (gcc version 4.8.5 (GCC) ) #1 SMP Thu Aug 17 15:34:57 +05 2023
 +
 +MediaTek SoC: MT7621A, RevID: 0103, RAM: DDR3, XTAL: 40MHz
 +CPU/OCP/SYS frequency: 880/293/220 MHz
 +CPU revision is: 0001992f (MIPS 1004Kc)
 +Determined physical RAM map:
 + memory: 08000000 @ 00000000 (usable)
 +Detected 3 available secondary CPU(s)
 +Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
 +Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
 +MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
 +Zone PFN ranges:
 +  DMA      0x00000000 -> 0x00001000
 +  Normal   0x00001000 -> 0x00008000
 +Movable zone start PFN for each node
 +Early memory PFN ranges
 +    0: 0x00000000 -> 0x00008000
 +PERCPU: Embedded 7 pages/cpu @814e9000 s4544 r8192 d15936 u32768
 +Built 1 zonelists in Zone order, mobility grouping off.  Total pages: 32512
 +Kernel command line: console=ttyS0,57600n8 root=/dev/mtdblock4 rootfstype=squashfs
 +PID hash table entries: 512 (order: -1, 2048 bytes)
 +Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
 +Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
 +Writing ErrCtl register=00011244
 +Readback ErrCtl register=00011244
 +Memory: 125796k/131072k available (3013k kernel code, 5276k reserved, 645k data, 240k init, 0k highmem)
 +start_kernel(): bug: interrupts were enabled *very* early, fixing it
 +Hierarchical RCU implementation.
 +NR_IRQS:72
 +MIPS GIC RevID: 3.0
 +Setting up vectored interrupts
 +console [ttyS0] enabled
 +Calibrating delay loop... 577.53 BogoMIPS (lpj=288768)
 +pid_max: default: 32768 minimum: 301
 +Mount-cache hash table entries: 512
 +Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
 +Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
 +MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
 +CPU revision is: 0001992f (MIPS 1004Kc)
 +Synchronize counters for CPU 1: done.
 +Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
 +Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
 +MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
 +CPU revision is: 0001992f (MIPS 1004Kc)
 +Synchronize counters for CPU 2: done.
 +Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
 +Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
 +MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
 +CPU revision is: 0001992f (MIPS 1004Kc)
 +Synchronize counters for CPU 3: done.
 +Brought up 4 CPUs
 +NET: Registered protocol family 16
 +bio: create slab <bio-0> at 0
 +SCSI subsystem initialized
 +PCI host bridge to bus 0000:00
 +pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
 +pci_bus 0000:00: root bus resource [io  0x1e160000-0x1e16ffff]
 +pci 0000:00:00.0: BAR 0: can't assign mem (size 0x80000000)
 +pci 0000:00:01.0: BAR 0: can't assign mem (size 0x80000000)
 +pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
 +pci 0000:00:01.0: BAR 9: assigned [mem 0x60100000-0x602fffff pref]
 +pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x600fffff]
 +pci 0000:00:00.0: PCI bridge to [bus 01-01]
 +pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
 +pci 0000:02:00.0: BAR 0: assigned [mem 0x60100000-0x601fffff 64bit pref]
 +pci 0000:02:00.0: BAR 2: assigned [mem 0x60200000-0x60203fff 64bit pref]
 +pci 0000:02:00.0: BAR 4: assigned [mem 0x60204000-0x60204fff 64bit pref]
 +pci 0000:00:01.0: PCI bridge to [bus 02-02]
 +pci 0000:00:01.0:   bridge window [mem 0x60100000-0x602fffff pref]
 +Switching to clocksource GIC
 +FS-Cache: Loaded
 +CacheFiles: Loaded
 +NET: Registered protocol family 1
 +NET: Registered protocol family 2
 +IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
 +TCP established hash table entries: 4096 (order: 3, 32768 bytes)
 +TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
 +TCP: Hash tables configured (established 4096 bind 4096)
 +TCP: reno registered
 +UDP hash table entries: 128 (order: 0, 4096 bytes)
 +4 CPUs re-calibrate udelay (lpj = 288768)
 +Load Ralink WDG Timer Module
 +squashfs: version 4.0 (2009/01/31) Phillip Lougher
 +msgmni has been set to 245
 +Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
 +io scheduler noop registered (default)
 +Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
 +serial8250: ttyS0 at MMIO 0x1e000c00 (irq = 34) is a 16550A
 +Ralink gpio driver initialized
 +loop: module loaded
 +MediaTek SPI flash driver, SPI clock: 44MHz
 +SPI flash chip: EN25QH128A (1c 70181c70) (16384 Kbytes)
 +Creating 7 MTD partitions on "raspi":
 +0x000000000000-0x000000030000 : "Bootloader"
 +0x000000030000-0x000000040000 : "Config"
 +0x000000040000-0x000000050000 : "Factory"
 +0x000000050000-0x00000019672e : "Kernel_stub"
 +0x00000019672e-0x000000f00000 : "RootFS_stub"
 +0x000000f00000-0x000001000000 : "RW-FS"
 +0x000000050000-0x000000f00000 : "Kernel_RootFS"
 +Ralink APSoC Ethernet Driver v3.2.4 (raeth)
 +raeth: PDMA RX ring 512, QDMA TX pool 1024. Max packet size 1536
 +raeth: NAPI & GRO support, weight 128
 +raeth: Byte Queue Limits (BQL) support
 +PPP generic driver version 2.4.2
 +PPP vpn led has gpio 14
 +PPP MPPE Compression module registered
 +NET: Registered protocol family 24
 +PPTP driver version 0.8.5
 +8021q: 802.1Q VLAN Support v1.8
 +NET: Registered protocol family 17
 +Netfilter messages via NETLINK v0.30.
 +nf_conntrack version 0.5.0 (16384 buckets, 32768 max)
 +gre: GRE over IPv4 demultiplexor driver
 +ip_tables: (C) 2000-2006 Netfilter Core Team
 +TCP: cubic registered
 +NET: Registered protocol family 10
 +ip6_tables: (C) 2000-2006 Netfilter Core Team
 +L2TP core driver, V2.0
 +PPPoL2TP kernel driver, V2.0
 +L2TP netlink interface
 +Registering the dns_resolver key type
 +NVRAM: Kernel NVRAM start init.
 +NVRAM: Particion 0 CRC cc192a30 OK.
 +VFS: Mounted root (squashfs filesystem) readonly on device 31:4.
 +mount /proc file system ok!
 +mount /sys file system ok!
 +mount /dev file system ok!
 +mount /var file system ok!
 +Freeing unused kernel memory: 240k freed
 +Build the /dev/console node.
 +Algorithmics/MIPS FPU Emulator v1.5
 +init started: BusyBox v1.34.1 ()
 +INIT Touch mdev.
 +INIT Mount /tmp/rootfs
 +INIT Create some persistent nodes in dev.
 +Start buttons service. Reset timeout = 10
 +Jan  1 00:00:03 haveged: haveged starting up
 +INIT Init RW particion
 +INIT RW File system is ok - preparing.
 +INIT Create start services trees
 +INIT Start 1st stages services now
 +~ # preconfigure >>>>>>>>>>>> NORMAL BOOT <<<<<<<<<<<<<<<
 +preconfigure Factory mac adresess: F8:F0:82:F7:B4:15 F8:F0:82:F7:B4:16 F8:F0:82:F7:B4:17 F8:F0:82:F7:B4:18
 +SYSLOG Start klogd
 +SYSLOG Start syslogd local
 +chpasswd: password for 'Admin' changed
 +Restore time to build time or save time.
 +Thu Aug 17 15:45:00 YEKT 2023
 +raeth: HW IP/TCP/UDP checksum RX/TX offload enabled
 +raeth: HW VLAN TX offload enabled
 +raeth: HW Scatter/Gather TX offload enabled
 +ESW: Link Status Changed - Port3 Link Up
 +Build config for fist WiFi module.
 +Build config for second WiFi module.
 +PCI: Enabling device 0000:01:00.0 (0000 -> 0002)
 +MT7603 AP Driver version: 4.1.0.0.P54
 +PCI: Enabling device 0000:02:00.0 (0000 -> 0002)
 +MT7603 Andes FW Version: ap_pcie
 +MT7603 Andes FW Build Date: 20160107100755
 +RTMPSetProfileParameters: Mcast frame, i=0,  Mode=2!
 +RTMPSetProfileParameters: Mcast frame, i=0,  MCS=3!
 +efuse_probe: efuse = 511161
 +RTMPSetProfileParameters: Mcast frame, i=0,  Mode=2!
 +RTMPSetProfileParameters: Mcast frame, i=0,  MCS=3!
 +INIT REDUCE TCP ACK, rai0
 +raeth: HW IP/TCP/UDP checksum RX/TX offload enabled
 +raeth: HW VLAN TX offload enabled
 +raeth: HW Scatter/Gather TX offload enabled
 +raeth: HW IP/TCP/UDP checksum RX/TX offload enabled
 +raeth: HW VLAN TX offload enabled
 +raeth: HW Scatter/Gather TX offload enabled
 +EXIT REDUCE TCP ACK, rai0
 +RTMPSetProfileParameters: Mcast frame, i=0,  Mode=2!
 +RTMPSetProfileParameters: Mcast frame, i=0,  MCS=3!
 +efuse_probe: efuse = 511161
 +RTMPSetProfileParameters: Mcast frame, i=0,  Mode=2!
 +RTMPSetProfileParameters: Mcast frame, i=0,  MCS=3!
 +INIT REDUCE TCP ACK, rai0
 +ESW: Link Status Changed - Port3 Link Down
 +
 + Set_Led_Proc ==> arg = 01-00-00-00-02-00-00-02
 +
 +Set_Led_Proc
 +01
 +00
 +00
 +00
 +02
 +00
 +00
 +02
 +
 + Set_Led_Proc ==> arg = 01-00-00-00-02-00-00-02
 +
 +Set_Led_Proc
 +01
 +00
 +00
 +00
 +02
 +00
 +00
 +02
 +ESW: Link Status Changed - Port3 Link Up
 +Ralink HW NAT v2.52.0 Module Enabled, FoE Size: 16384
 +IRQ 64 was BANNED.
 +IRQ 65 was BANNED.
 +IRQ 66 was BANNED.
 +IRQ 67 was BANNED.
 +IRQ 68 was BANNED.
 +IRQ 69 was BANNED.
 +IRQ 70 was BANNED.
 +IRQ 71 was BANNED.
 +IRQ 12 was BANNED.
 +IRQ 32 was BANNED.
 +</nowiki>
 +</WRAP>
 +
 +fw version - SNR-CPE-ME2-Lite-WRT-2.6.2-2411080916-1a9bc5ee2.bin:
 <WRAP bootlog> <WRAP bootlog>
 <nowiki> <nowiki>
  • Last modified: 2024/12/18 15:02
  • by frollic