Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
| toh:snr:cpe-me2-lite [2024/12/11 13:10] – [Serial] wertwert4pda | toh:snr:cpe-me2-lite [2024/12/18 15:02] (current) – [Info] frollic | ||
|---|---|---|---|
| Line 12: | Line 12: | ||
| {{media: | {{media: | ||
| + | {{media: | ||
| ===== Supported Versions ===== | ===== Supported Versions ===== | ||
| Line 81: | Line 82: | ||
| -> [[docs: | -> [[docs: | ||
| - | FIXME Please add the installation procedure here. | + | |
| ==== Flash Layout ==== | ==== Flash Layout ==== | ||
| Line 102: | Line 103: | ||
| <WRAP BOX> | <WRAP BOX> | ||
| - | FIXME //The instructions below are for Broadcom devices and only serve as an example.// | ||
| - | **//Remove / modify them if they do not apply to this particular device!//** | ||
| - | |||
| This section deals with | This section deals with | ||
| * How you install OpenWrt from a device freshly opened | * How you install OpenWrt from a device freshly opened | ||
| Line 110: | Line 108: | ||
| **Note:** Reset router to factory defaults if it has been previously configured. | **Note:** Reset router to factory defaults if it has been previously configured. | ||
| - | | + | |
| - | * Upload | + | **Flash instruction via WEB (old factory firmware 1.10.x)** |
| - | | + | 1. Boot SNR-CPE-ME2-Lite normally with " |
| - | * Telnet to 192.168.1.1 and set a root password, or browse | + | 2. Access |
| + | 3. Select the OpenWrt sysupgrade image in " | ||
| + | | ||
| + | |||
| + | **Note: For new factory firmware (EasyWRT 2.6.x) need downgrade | ||
| + | |||
| </ | </ | ||
| Line 127: | Line 130: | ||
| ^ Bootloader MAC address (special) | ^ Bootloader MAC address (special) | ||
| ^ Firmware tftp image | [[: | ^ Firmware tftp image | [[: | ||
| - | ^ TFTP transfer window | + | ^ TFTP transfer window |
| - | ^ TFTP window start | approximately | + | ^ TFTP window start | approximately |
| - | ^ TFTP client required IP address | + | ^ TFTP client required IP address |
| </ | </ | ||
| Line 137: | Line 140: | ||
| <WRAP BOX> | <WRAP BOX> | ||
| - | |||
| - | FIXME These are generic instructions. Update with your router' | ||
| ==== LuCI Web Upgrade Process ==== | ==== LuCI Web Upgrade Process ==== | ||
| Line 149: | Line 150: | ||
| If you don't have a GUI (LuCI) available, you can alternatively upgrade via the command line. | If you don't have a GUI (LuCI) available, you can alternatively upgrade via the command line. | ||
| - | There are two command line methods for upgrading: | ||
| - | |||
| - | * '' | ||
| - | * '' | ||
| Note: It is important that you put the firmware image into the ramdisk (/tmp) before you start flashing. | Note: It is important that you put the firmware image into the ramdisk (/tmp) before you start flashing. | ||
| Line 164: | Line 161: | ||
| wget http:// | wget http:// | ||
| sysupgrade / | sysupgrade / | ||
| - | </ | ||
| - | |||
| - | === mtd === | ||
| - | |||
| - | If '' | ||
| - | |||
| - | * Login as root via SSH on 192.168.1.1, | ||
| - | |||
| - | < | ||
| - | cd /tmp | ||
| - | wget http:// | ||
| - | mtd write / | ||
| </ | </ | ||
| Line 224: | Line 209: | ||
| ===== Hardware ===== | ===== Hardware ===== | ||
| ==== Info ==== | ==== Info ==== | ||
| - | <WRAP BOX> | + | ==== Info ==== |
| - | FIXME | + | |
| - | - This table is automatically generated, **once the correct filters for Brand and Model are set.** | + | |
| - | - If you see " | + | |
| - | - If you still don't see a table here, or a table filled with ' | + | |
| - | - If you see a table with the desired device data, everything is OK and you can delete this text and the ''< | + | |
| - | - If it still doesn' | + | |
| - | </ | + | |
| - | ---- datatemplatelist dttpllist ---- | ||
| - | template: meta: | ||
| - | cols : Brand, Model, Versions, Device Type, Availability, | ||
| - | filter | ||
| - | filter | ||
| - | filter | ||
| - | ---- | ||
| + | <!-- ToH: { | ||
| + | " | ||
| + | " | ||
| + | " | ||
| + | " | ||
| + | " | ||
| + | " | ||
| + | } --> | ||
| ==== Photos ==== | ==== Photos ==== | ||
| /* =====>>>>> | /* =====>>>>> | ||
| Line 261: | Line 240: | ||
| <WRAP BOX> | <WRAP BOX> | ||
| - | FIXME //Describe what needs to be done to open the device, e.g. remove rubber feet, adhesive labels, screws, ...// | + | |
| - | | + | - Unscrew the 4 Phillips screws from the bottom of the device. |
| + | - There are 6 latches around the perimeter between the halves of the case. They need to be pressed by inserting | ||
| </ | </ | ||
| + | {{media: | ||
| //Main PCB://\\ | //Main PCB://\\ | ||
| - | **Insert photo of PCB** | + | {{media: |
| + | |||
| + | //Chips on board:// | ||
| + | {{media: | ||
| + | |||
| + | // | ||
| + | {{media: | ||
| ==== Serial ==== | ==== Serial ==== | ||
| Line 292: | Line 280: | ||
| ===== Bootlogs ===== | ===== Bootlogs ===== | ||
| ==== OEM bootlog ==== | ==== OEM bootlog ==== | ||
| + | fw version - SNR-CPE-ME2-Lite-1.10.9.1708231534.bin: | ||
| + | <WRAP bootlog> | ||
| + | < | ||
| + | =================================================================== | ||
| + | MT7621 | ||
| + | CPU=500000000 HZ BUS=166666666 HZ | ||
| + | ================================================================== | ||
| + | Change MPLL source from XTAL to CR... | ||
| + | do MEMPLL setting.. | ||
| + | MEMPLL Config : 0x11100000 | ||
| + | 3PLL mode + External loopback | ||
| + | === XTAL-40Mhz === DDR-1200Mhz === | ||
| + | PLL2 FB_DL: 0xf, 1/0 = 556/468 3D000000 | ||
| + | PLL3 FB_DL: 0xf, 1/0 = 650/374 3D000000 | ||
| + | PLL4 FB_DL: 0x16, 1/0 = 548/476 59000000 | ||
| + | do DDR setting..[01F40000] | ||
| + | Apply DDR3 Setting...(use customer AC) | ||
| + | 0 8 | ||
| + | -------------------------------------------------------------------------------- | ||
| + | 0000: | ||
| + | 0001: | ||
| + | 0002: | ||
| + | 0003: | ||
| + | 0004: | ||
| + | 0005: | ||
| + | 0006: | ||
| + | 0007: | ||
| + | 0008: | ||
| + | 0009: | ||
| + | 000A: | ||
| + | 000B: | ||
| + | 000C: | ||
| + | 000D: | ||
| + | 000E: | ||
| + | 000F: | ||
| + | 0010: | ||
| + | 0011: | ||
| + | 0012: | ||
| + | 0013: | ||
| + | 0014: | ||
| + | 0015: | ||
| + | 0016: | ||
| + | 0017: | ||
| + | 0018: | ||
| + | 0019: | ||
| + | 001A: | ||
| + | 001B: | ||
| + | 001C: | ||
| + | 001D: | ||
| + | 001E: | ||
| + | 001F: | ||
| + | DRAMC_DQSCTL1[0e0]=13000000 | ||
| + | DRAMC_DQSGCTL[124]=80000033 | ||
| + | rank 0 coarse = 15 | ||
| + | rank 0 fine = 48 | ||
| + | B:| 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 | ||
| + | opt_dle value:11 | ||
| + | DRAMC_DDR2CTL[07c]=C287223D | ||
| + | DRAMC_PADCTL4[0e4]=000022B3 | ||
| + | DRAMC_DQIDLY1[210]=0F0F0C0F | ||
| + | DRAMC_DQIDLY2[214]=0D0F0E0F | ||
| + | DRAMC_DQIDLY3[218]=0C0E090C | ||
| + | DRAMC_DQIDLY4[21c]=0C0C0E0B | ||
| + | DRAMC_R0DELDLY[018]=00002020 | ||
| + | ================================================================== | ||
| + | RX DQS perbit delay software calibration | ||
| + | ================================================================== | ||
| + | 1.0-15 bit dq delay value | ||
| + | ================================================================== | ||
| + | bit| | ||
| + | -------------------------------------- | ||
| + | 0 | 14 11 14 13 12 11 15 13 11 9 | ||
| + | 10 | 12 11 9 12 10 9 | ||
| + | -------------------------------------- | ||
| + | |||
| + | ================================================================== | ||
| + | 2.dqs window | ||
| + | x=pass dqs delay value (min~max)center | ||
| + | y=0-7bit DQ of every group | ||
| + | input delay:DQS0 =32 DQS1 = 32 | ||
| + | ================================================================== | ||
| + | bit | ||
| + | 0 (1~60)30 | ||
| + | 1 (1~61)31 | ||
| + | 2 (1~59)30 | ||
| + | 3 (1~60)30 | ||
| + | 4 (0~59)29 | ||
| + | 5 (0~59)29 | ||
| + | 6 (1~59)30 | ||
| + | 7 (3~62)32 | ||
| + | ================================================================== | ||
| + | 3.dq delay value last | ||
| + | ================================================================== | ||
| + | bit| 0 1 2 3 4 5 6 7 8 9 | ||
| + | -------------------------------------- | ||
| + | 0 | 15 12 15 15 15 14 15 13 12 9 | ||
| + | 10 | 14 12 11 14 12 12 | ||
| + | ================================================================== | ||
| + | ================================================================== | ||
| + | | ||
| + | ================================================================== | ||
| + | DQS loop = 15, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[0]=15, | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[1]=15, | ||
| + | DQ loop=15, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqdly_pass[0]=15, | ||
| + | dqs_perbyte_dly.last_dqdly_pass[1]=15, | ||
| + | byte:0, (DQS, | ||
| + | byte:1, (DQS, | ||
| + | DRAMC_DQODLY1[200]=88888888 | ||
| + | DRAMC_DQODLY2[204]=88888888 | ||
| + | 20,data:88 | ||
| + | [EMI] DRAMC calibration passed | ||
| + | |||
| + | =================================================================== | ||
| + | MT7621 | ||
| + | CPU=500000000 HZ BUS=166666666 HZ | ||
| + | =================================================================== | ||
| + | |||
| + | |||
| + | U-Boot 1.1.3 (Jun 25 2020 - 13:46:13) | ||
| + | |||
| + | Board: MediaTek APSoC DRAM: 128 MB | ||
| + | |||
| + | Config XHCI 40M PLL | ||
| + | ****************************** | ||
| + | Software System Reset Occurred | ||
| + | ****************************** | ||
| + | MediaTek SPI flash driver, SPI clock: 31MHz | ||
| + | spi device id: 1c 70 18 1c | ||
| + | find flash: EN25QH128A | ||
| + | *** Warning - bad CRC, using default environment | ||
| + | |||
| + | ============================================ | ||
| + | MediaTek U-Boot Version: 5.0.1.0-6 | ||
| + | -------------------------------------------- | ||
| + | ASIC MT7621A DualCore (MAC to MT7530 Mode) | ||
| + | DRAM_CONF_FROM: | ||
| + | DRAM_TYPE: DDR3 | ||
| + | DRAM bus: 16 bit | ||
| + | Xtal Mode=3 OCP Ratio=1/3 | ||
| + | Flash component: SPI Flash | ||
| + | Date:Jun 25 2020 Time: | ||
| + | ============================================ | ||
| + | icache: sets:256, ways:4, linesz:32, total:32768 | ||
| + | dcache: sets:256, ways:4, linesz:32, total:32768 | ||
| + | |||
| + | #### The CPU freq = 880 MHZ #### | ||
| + | | ||
| + | |||
| + | Reset MT7530 | ||
| + | set LAN/WAN WLLLL | ||
| + | |||
| + | Please choose the operation: | ||
| + | 0: Load system code then write to Flash via Serial. | ||
| + | 1: Load system code to SDRAM via TFTP. | ||
| + | 2: Load system code then write to Flash via TFTP. | ||
| + | 3: Boot system code via Flash (default). | ||
| + | 4: Enter boot command line interface. | ||
| + | 7: Load U-Boot code then write to Flash via Serial. | ||
| + | 9: Load U-Boot code then write to Flash via TFTP. 0 | ||
| + | |||
| + | |||
| + | 3: System Boot system code via Flash. | ||
| + | ## Checking image at bc050000 ... | ||
| + | Image Name: | ||
| + | Image Type: MIPS Linux Kernel Image (lzma compressed) | ||
| + | Data Size: 12040042 Bytes = 11.5 MB | ||
| + | Load Address: 81001000 | ||
| + | Entry Point: | ||
| + | | ||
| + | | ||
| + | No initrd | ||
| + | ## Transferring control to Linux (at address 812e0300) ... | ||
| + | ## Giving linux memsize in MB, 128 | ||
| + | |||
| + | Starting kernel ... | ||
| + | |||
| + | 6 | ||
| + | LINUX started... | ||
| + | DetectRAMsequence | ||
| + | MAX memory: | ||
| + | RAM size detected: | ||
| + | FullviewRAM: | ||
| + | Linux version 3.4.113.185 (sfstudio_at_mail.ru@wive-ng.sf.net) (gcc version 4.8.5 (GCC) ) #1 SMP Thu Aug 17 15:34:57 +05 2023 | ||
| + | |||
| + | MediaTek SoC: MT7621A, RevID: 0103, RAM: DDR3, XTAL: 40MHz | ||
| + | CPU/OCP/SYS frequency: 880/293/220 MHz | ||
| + | CPU revision is: 0001992f (MIPS 1004Kc) | ||
| + | Determined physical RAM map: | ||
| + | | ||
| + | Detected 3 available secondary CPU(s) | ||
| + | Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | Zone PFN ranges: | ||
| + | DMA 0x00000000 -> 0x00001000 | ||
| + | Normal | ||
| + | Movable zone start PFN for each node | ||
| + | Early memory PFN ranges | ||
| + | 0: 0x00000000 -> 0x00008000 | ||
| + | PERCPU: Embedded 7 pages/cpu @814e9000 s4544 r8192 d15936 u32768 | ||
| + | Built 1 zonelists in Zone order, mobility grouping off. Total pages: 32512 | ||
| + | Kernel command line: console=ttyS0, | ||
| + | PID hash table entries: 512 (order: -1, 2048 bytes) | ||
| + | Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) | ||
| + | Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) | ||
| + | Writing ErrCtl register=00011244 | ||
| + | Readback ErrCtl register=00011244 | ||
| + | Memory: 125796k/ | ||
| + | start_kernel(): | ||
| + | Hierarchical RCU implementation. | ||
| + | NR_IRQS:72 | ||
| + | MIPS GIC RevID: 3.0 | ||
| + | Setting up vectored interrupts | ||
| + | console [ttyS0] enabled | ||
| + | Calibrating delay loop... 577.53 BogoMIPS (lpj=288768) | ||
| + | pid_max: default: 32768 minimum: 301 | ||
| + | Mount-cache hash table entries: 512 | ||
| + | Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | CPU revision is: 0001992f (MIPS 1004Kc) | ||
| + | Synchronize counters for CPU 1: done. | ||
| + | Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | CPU revision is: 0001992f (MIPS 1004Kc) | ||
| + | Synchronize counters for CPU 2: done. | ||
| + | Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | CPU revision is: 0001992f (MIPS 1004Kc) | ||
| + | Synchronize counters for CPU 3: done. | ||
| + | Brought up 4 CPUs | ||
| + | NET: Registered protocol family 16 | ||
| + | bio: create slab < | ||
| + | SCSI subsystem initialized | ||
| + | PCI host bridge to bus 0000:00 | ||
| + | pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] | ||
| + | pci_bus 0000:00: root bus resource [io 0x1e160000-0x1e16ffff] | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | Switching to clocksource GIC | ||
| + | FS-Cache: Loaded | ||
| + | CacheFiles: Loaded | ||
| + | NET: Registered protocol family 1 | ||
| + | NET: Registered protocol family 2 | ||
| + | IP route cache hash table entries: 1024 (order: 0, 4096 bytes) | ||
| + | TCP established hash table entries: 4096 (order: 3, 32768 bytes) | ||
| + | TCP bind hash table entries: 4096 (order: 3, 32768 bytes) | ||
| + | TCP: Hash tables configured (established 4096 bind 4096) | ||
| + | TCP: reno registered | ||
| + | UDP hash table entries: 128 (order: 0, 4096 bytes) | ||
| + | 4 CPUs re-calibrate udelay (lpj = 288768) | ||
| + | Load Ralink WDG Timer Module | ||
| + | squashfs: version 4.0 (2009/ | ||
| + | msgmni has been set to 245 | ||
| + | Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254) | ||
| + | io scheduler noop registered (default) | ||
| + | Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled | ||
| + | serial8250: ttyS0 at MMIO 0x1e000c00 (irq = 34) is a 16550A | ||
| + | Ralink gpio driver initialized | ||
| + | loop: module loaded | ||
| + | MediaTek SPI flash driver, SPI clock: 44MHz | ||
| + | SPI flash chip: EN25QH128A (1c 70181c70) (16384 Kbytes) | ||
| + | Creating 7 MTD partitions on " | ||
| + | 0x000000000000-0x000000030000 : " | ||
| + | 0x000000030000-0x000000040000 : " | ||
| + | 0x000000040000-0x000000050000 : " | ||
| + | 0x000000050000-0x00000019672e : " | ||
| + | 0x00000019672e-0x000000f00000 : " | ||
| + | 0x000000f00000-0x000001000000 : " | ||
| + | 0x000000050000-0x000000f00000 : " | ||
| + | Ralink APSoC Ethernet Driver v3.2.4 (raeth) | ||
| + | raeth: PDMA RX ring 512, QDMA TX pool 1024. Max packet size 1536 | ||
| + | raeth: NAPI & GRO support, weight 128 | ||
| + | raeth: Byte Queue Limits (BQL) support | ||
| + | PPP generic driver version 2.4.2 | ||
| + | PPP vpn led has gpio 14 | ||
| + | PPP MPPE Compression module registered | ||
| + | NET: Registered protocol family 24 | ||
| + | PPTP driver version 0.8.5 | ||
| + | 8021q: 802.1Q VLAN Support v1.8 | ||
| + | NET: Registered protocol family 17 | ||
| + | Netfilter messages via NETLINK v0.30. | ||
| + | nf_conntrack version 0.5.0 (16384 buckets, 32768 max) | ||
| + | gre: GRE over IPv4 demultiplexor driver | ||
| + | ip_tables: (C) 2000-2006 Netfilter Core Team | ||
| + | TCP: cubic registered | ||
| + | NET: Registered protocol family 10 | ||
| + | ip6_tables: (C) 2000-2006 Netfilter Core Team | ||
| + | L2TP core driver, V2.0 | ||
| + | PPPoL2TP kernel driver, V2.0 | ||
| + | L2TP netlink interface | ||
| + | Registering the dns_resolver key type | ||
| + | NVRAM: Kernel NVRAM start init. | ||
| + | NVRAM: Particion 0 CRC cc192a30 OK. | ||
| + | VFS: Mounted root (squashfs filesystem) readonly on device 31:4. | ||
| + | mount /proc file system ok! | ||
| + | mount /sys file system ok! | ||
| + | mount /dev file system ok! | ||
| + | mount /var file system ok! | ||
| + | Freeing unused kernel memory: 240k freed | ||
| + | Build the / | ||
| + | Algorithmics/ | ||
| + | init started: BusyBox v1.34.1 () | ||
| + | INIT Touch mdev. | ||
| + | INIT Mount /tmp/rootfs | ||
| + | INIT Create some persistent nodes in dev. | ||
| + | Start buttons service. Reset timeout = 10 | ||
| + | Jan 1 00:00:03 haveged: haveged starting up | ||
| + | INIT Init RW particion | ||
| + | INIT RW File system is ok - preparing. | ||
| + | INIT Create start services trees | ||
| + | INIT Start 1st stages services now | ||
| + | ~ # preconfigure >>>>>>>>>>>> | ||
| + | preconfigure Factory mac adresess: F8: | ||
| + | SYSLOG Start klogd | ||
| + | SYSLOG Start syslogd local | ||
| + | chpasswd: password for ' | ||
| + | Restore time to build time or save time. | ||
| + | Thu Aug 17 15:45:00 YEKT 2023 | ||
| + | raeth: HW IP/TCP/UDP checksum RX/TX offload enabled | ||
| + | raeth: HW VLAN TX offload enabled | ||
| + | raeth: HW Scatter/ | ||
| + | ESW: Link Status Changed - Port3 Link Up | ||
| + | Build config for fist WiFi module. | ||
| + | Build config for second WiFi module. | ||
| + | PCI: Enabling device 0000: | ||
| + | MT7603 AP Driver version: 4.1.0.0.P54 | ||
| + | PCI: Enabling device 0000: | ||
| + | MT7603 Andes FW Version: ap_pcie | ||
| + | MT7603 Andes FW Build Date: 20160107100755 | ||
| + | RTMPSetProfileParameters: | ||
| + | RTMPSetProfileParameters: | ||
| + | efuse_probe: | ||
| + | RTMPSetProfileParameters: | ||
| + | RTMPSetProfileParameters: | ||
| + | INIT REDUCE TCP ACK, rai0 | ||
| + | raeth: HW IP/TCP/UDP checksum RX/TX offload enabled | ||
| + | raeth: HW VLAN TX offload enabled | ||
| + | raeth: HW Scatter/ | ||
| + | raeth: HW IP/TCP/UDP checksum RX/TX offload enabled | ||
| + | raeth: HW VLAN TX offload enabled | ||
| + | raeth: HW Scatter/ | ||
| + | EXIT REDUCE TCP ACK, rai0 | ||
| + | RTMPSetProfileParameters: | ||
| + | RTMPSetProfileParameters: | ||
| + | efuse_probe: | ||
| + | RTMPSetProfileParameters: | ||
| + | RTMPSetProfileParameters: | ||
| + | INIT REDUCE TCP ACK, rai0 | ||
| + | ESW: Link Status Changed - Port3 Link Down | ||
| + | |||
| + | | ||
| + | |||
| + | Set_Led_Proc | ||
| + | 01 | ||
| + | 00 | ||
| + | 00 | ||
| + | 00 | ||
| + | 02 | ||
| + | 00 | ||
| + | 00 | ||
| + | 02 | ||
| + | |||
| + | | ||
| + | |||
| + | Set_Led_Proc | ||
| + | 01 | ||
| + | 00 | ||
| + | 00 | ||
| + | 00 | ||
| + | 02 | ||
| + | 00 | ||
| + | 00 | ||
| + | 02 | ||
| + | ESW: Link Status Changed - Port3 Link Up | ||
| + | Ralink HW NAT v2.52.0 Module Enabled, FoE Size: 16384 | ||
| + | IRQ 64 was BANNED. | ||
| + | IRQ 65 was BANNED. | ||
| + | IRQ 66 was BANNED. | ||
| + | IRQ 67 was BANNED. | ||
| + | IRQ 68 was BANNED. | ||
| + | IRQ 69 was BANNED. | ||
| + | IRQ 70 was BANNED. | ||
| + | IRQ 71 was BANNED. | ||
| + | IRQ 12 was BANNED. | ||
| + | IRQ 32 was BANNED. | ||
| + | </ | ||
| + | </ | ||
| + | |||
| + | fw version - SNR-CPE-ME2-Lite-WRT-2.6.2-2411080916-1a9bc5ee2.bin: | ||
| <WRAP bootlog> | <WRAP bootlog> | ||
| < | < | ||