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toh:snr:cpe-me2-lite [2024/12/10 10:13] – [OEM bootlog] wertwert4pdatoh:snr:cpe-me2-lite [2024/12/11 14:41] – [OEM easy installation] wertwert4pda
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 /* USE https://openwrt.org/meta/create_new_device_page */ /* USE https://openwrt.org/meta/create_new_device_page */
  
-{{page>meta:infobox:construction&noheader&nofooter&noeditbtn}} +Wi-Fi Mesh router AC1200IEEE 802.11 a/b/g/n/ac 1GE WAN 4 GE LANIPv6IGMP, TR-069
- +
-//Write a shortrelevant description of the deviceInclude technical overview, but avoid marketing buzzwords/useless stuff. Two to four sentences is about right. A picture is good, too. Edit the page to see how to add pictures.// +
- +
-<WRAP BOX> +
-FIXME Any text with a light background (like this one) provides instructions for creating the Details PageWhen you have filled in correct/useful information (instead of any template that's there) **remove the instructionsas well as the ''<nowiki><WRAP></nowiki>'' that encloses it.** +
-</WRAP>+
  
 /*****/ /*****/
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 /*****/ /*****/
  
-{{media:example:genericrouter1.png?200|Generic Router}} +{{media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b.jpg?400|SNR CPE-ME2-Lite Router}} 
- +{{media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-all.jpg?400}}
-<WRAP BOX> +
-FIXME +
-===== Getting started with a new Device Page ===== +
-  This is an empty template that suggests the information that should be present on a well-constructed Device Page. This means, that **you have to fill it with life and information.** +
-  There are several "fixme" tags with text on a light background (like this text) throughout this template. As you fill in the page, remove those tags so that people can judge its completeness. +
-  When there are no more "fixme" tags left, delete this one too, along with the ''<nowiki><WRAP></nowiki>'' that encloses it. +
- +
-===== Keep the articles modular ===== +
-  * Please include only model specific information, omit bla,bla and put everything generic into separate articles +
-  * If you have no time to write certain stuff, link to [[docs:start]] +
-  * [[docs:guide-user:base-system:start]] should lead the way, do not explain this again +
-  * DO NOT provide a complete howto here! Instead //groom// the [[docs:start|general documentation]]. +
-</WRAP>+
  
 ===== Supported Versions ===== ===== Supported Versions =====
- 
-<WRAP BOX> 
-FIXME 
-  - The tables below are automatically generated, **once the correct filters for Brand and Model are set.** 
-  - If the tables below show information for ''<nowiki>SNR CPE-ME2-Lite </nowiki>'', everything is OK and you can delete this text and the ''<nowiki><WRAP></nowiki>'' that encloses it. 
-  - If the tables below contain "Nothing found", it means that either 
-    - the dataentry page for SNR CPE-ME2-Lite  is missing. Please [[meta:create_new_dataentry_page|create a new dataentry page]] first, then reload this page. The tables should then contain $something. If they do, delete this text and the ''<nowiki><WRAP></nowiki>'' that encloses it. 
-    - filters are not set correctly. Most common reason for "Nothing found": The dataentry does not contain a Version, but we are filtering here for version -> Please **edit this section and adjust the filters with the proper Brand, Model and Version.** In case the dataentry does not contain a version, delete the line ''filter  : Versions~''. Just try, it's easy. The tables should then contain $something. If they do, delete this text and the ''<nowiki><WRAP></nowiki>'' that encloses it. 
-  - If the tables still contain "Nothing found": Don't panic, calm down, take a deep breath and [[:contact|contact a wiki admin]] (tmomas) for help. 
-</WRAP> 
- 
 <!-- ToH: { <!-- ToH: {
   "source": "json",   "source": "json",
   "dom": "t",   "dom": "t",
   "paging": false,   "paging": false,
 +  "rotate": true,
   "shownColumns": ["brand", "model", "version", "supportedcurrentrel", "oemdevicehomepageurl", "forumsearch", "deviceid"],   "shownColumns": ["brand", "model", "version", "supportedcurrentrel", "oemdevicehomepageurl", "forumsearch", "deviceid"],
-  "filterColumns": {"brand": "^SNR$", "model": "^CPE-ME2-Lite$", "version": "^@@Version\\|@@$"}+  "filterColumns": {"brand": "^SNR$", "model": "^CPE-ME2-Lite$", "version": "^rev.B$"}
 } --> } -->
  
 /* If no unsupported functions known, comment out the following datatable or delete it. */ /* If no unsupported functions known, comment out the following datatable or delete it. */
-<!-- ToH: {+/* <!-- ToH: {
   "source": "json",   "source": "json",
   "dom": "t",   "dom": "t",
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   "shownColumns": ["unsupported_functions"],   "shownColumns": ["unsupported_functions"],
   "filterColumns": {"brand": "^SNR$", "model": "^CPE-ME2-Lite$", "version": "^@@Version\\|@@$"}   "filterColumns": {"brand": "^SNR$", "model": "^CPE-ME2-Lite$", "version": "^@@Version\\|@@$"}
-} -->+} --> */
  
 ===== Experimental Versions ===== ===== Experimental Versions =====
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   "dom": "t",   "dom": "t",
   "paging": false,   "paging": false,
 +  "rotate": true,
   "shownColumns": ["model", "version", "cpu", "cpumhz", "cpucores", "flashmb", "rammb", "wlanhardware", "wlan24ghz", "wlan50ghz", "ethernet100mports", "ethernet1gports", "modem", "usbports"],   "shownColumns": ["model", "version", "cpu", "cpumhz", "cpucores", "flashmb", "rammb", "wlanhardware", "wlan24ghz", "wlan50ghz", "ethernet100mports", "ethernet1gports", "modem", "usbports"],
-  "filterColumns": {"brand": "^SNR$", "model": "^CPE-ME2-Lite$", "version": "^@@Version\\|@@$"}+  "filterColumns": {"brand": "^SNR$", "model": "^CPE-ME2-Lite$", "version": "^rev.B$"}
 } --> } -->
  
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 ===== Installation ===== ===== Installation =====
 /* stable release */ /* stable release */
-/* uncomment once stable release is available+/* uncomment once stable release is available */
 <!-- ToH: { <!-- ToH: {
   "source": "json",   "source": "json",
   "dom": "t",   "dom": "t",
   "paging": false,   "paging": false,
 +  "rotate": true,
   "shownColumns": ["model", "version", "supportedcurrentrel", "firmwareopenwrtinstallurl", "firmwareopenwrtupgradeurl", "firmwareoemstockurl"],   "shownColumns": ["model", "version", "supportedcurrentrel", "firmwareopenwrtinstallurl", "firmwareopenwrtupgradeurl", "firmwareoemstockurl"],
-  "filterColumns": {"brand": "^SNR$", "model": "^CPE-ME2-Lite$", "version": "^@@Version\\|@@$"}+  "filterColumns": {"brand": "^SNR$", "model": "^CPE-ME2-Lite$", "version": "^rev.B$"}
 } --> } -->
-*/+
  
  
 /* snapshot */ /* snapshot */
-/* delete once stable release is available */+/* delete once stable release is available
 <!-- ToH: { <!-- ToH: {
   "source": "json",   "source": "json",
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   "paging": false,   "paging": false,
   "shownColumns": ["model", "version", "supportedcurrentrel", "firmwareopenwrtsnapshotinstallurl", "firmwareopenwrtsnapshotupgradeurl", "firmwareoemstockurl"],   "shownColumns": ["model", "version", "supportedcurrentrel", "firmwareopenwrtsnapshotinstallurl", "firmwareopenwrtsnapshotupgradeurl", "firmwareoemstockurl"],
-  "filterColumns": {"brand": "^SNR$", "model": "^CPE-ME2-Lite$", "version": "^@@Version\\|@@$"}+  "filterColumns": {"brand": "^SNR$", "model": "^CPE-ME2-Lite$", "version": "^^rev.B$"}
 } --> } -->
 + */
  
 -> [[docs:guide-user:installation:generic.flashing|Install OpenWrt (generic explanation)]] -> [[docs:guide-user:installation:generic.flashing|Install OpenWrt (generic explanation)]]
  
-FIXME Please add the installation procedure here.+
  
 ==== Flash Layout ==== ==== Flash Layout ====
 <WRAP BOX> <WRAP BOX>
-FIXME //[[:docs:techref:flash.layout#discovery_how_to_find_out|Find out flash layout]], then add the flash layout table here (copy, paste, modify the [[docs:techref:flash.layout#partitioning_of_the_flash|example]]).// +spi-nor spi0.0: en25qh128 (16384 Kbytes) 
- +<code> 
-Please check out the article [[docs:techref:flash.layout|Flash layout]]. It contains examples and explanations that describe how to document the flash layout.+cat /proc/mtd 
 +dev   size   erasesize  name 
 +mtd000030000 00010000 "u-boot" 
 +mtd100010000 00010000 "config" 
 +mtd200010000 00010000 "factory" 
 +mtd300fb0000 00010000 "firmware" 
 +mtd4: 00320767 00010000 "kernel" 
 +mtd500c8f899 00010000 "rootfs" 
 +mtd600840000 00010000 "rootfs_data" 
 +</code>
 </WRAP> </WRAP>
  
Line 121: Line 103:
  
 <WRAP BOX> <WRAP BOX>
-FIXME //The instructions below are for Broadcom devices and only serve as an example.//\\ 
-**//Remove / modify them if they do not apply to this particular device!//** 
- 
 This section deals with This section deals with
   * How you install OpenWrt from a device freshly opened   * How you install OpenWrt from a device freshly opened
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 **Note:** Reset router to factory defaults if it has been previously configured. **Note:** Reset router to factory defaults if it has been previously configured.
-  Browse to ''<nowiki>http://192.168.1.1/Upgrade.asp</nowiki>'' + 
-  * Upload .bin file to router +**Flash instruction via WEB (old factory firmware 1.10.x)*
-  Wait for it to reboot +    1. Boot SNR-CPE-ME2-Lite normally with "Router" mode 
-  Telnet to 192.168.1.1 and set a root password, or browse to ''<nowiki>http://192.168.1.1</nowiki>'' if LuCI is installed.+    2. Access to "http://192.168.1.1/" and open "Administration -Management" page 
 +    3Select the OpenWrt sysupgrade image in "Firmware update" section and click "Update" button 
 +    4. Wait ~120 seconds to complete flashing 
 + 
 +**Note: For new factory firmware (EasyWRT 2.6.x) need downgrade to old factory image firstIt possible from web interface.**  
 +   
 </WRAP> </WRAP>
  
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 <WRAP BOX> <WRAP BOX>
  
-FIXME Enter values for "FILL-IN" below +^ Bootloader tftp server IPv4 address 192.168.1.1   | 
- +^ Bootloader MAC address (special)     F8:F0:82:30:52:11  
-^ Bootloader tftp server IPv4 address FILL-IN   | +^ Firmware tftp image                  | [[:downloads|Latest OpenWrt release]] | 
-^ Bootloader MAC address (special)     FILL-IN   +^ TFTP transfer window                 10 seconds                            
-^ Firmware tftp image                  | [[:downloads|Latest OpenWrt release]] (**''NOTE:''** Name must contain //"tftp"//+^ TFTP window start                    | approximately 120 seconds after power on   | 
-^ TFTP transfer window                 FILL-IN seconds                                +^ TFTP client required IP address      | 192.168.1.131                                |
-^ TFTP window start                    | approximately FILL-IN seconds after power on   | +
-^ TFTP client required IP address      | FILL-IN                                        |+
  
 </WRAP> </WRAP>
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 <WRAP BOX> <WRAP BOX>
- 
-FIXME These are generic instructions. Update with your router's specifics. 
  
 ==== LuCI Web Upgrade Process ==== ==== LuCI Web Upgrade Process ====
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 If you don't have a GUI (LuCI) available, you can alternatively upgrade via the command line. If you don't have a GUI (LuCI) available, you can alternatively upgrade via the command line.
-There are two command line methods for upgrading: 
- 
-  * ''sysupgrade'' 
-  * ''mtd'' 
  
 Note: It is important that you put the firmware image into the ramdisk (/tmp) before you start flashing. Note: It is important that you put the firmware image into the ramdisk (/tmp) before you start flashing.
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 wget http://downloads.openwrt.org/snapshots/trunk/XXX/xxx.abc wget http://downloads.openwrt.org/snapshots/trunk/XXX/xxx.abc
 sysupgrade /tmp/xxx.abc sysupgrade /tmp/xxx.abc
-</code> 
- 
-=== mtd === 
- 
-If ''sysupgrade'' does not support this router, use ''mtd''. 
- 
-  * Login as root via SSH on 192.168.1.1, then enter the following commands: 
- 
-<code> 
-cd /tmp 
-wget http://downloads.openwrt.org/snapshots/trunk/XXX/xxx.abc 
-mtd write /tmp/xxx.abc linux && reboot 
 </code> </code>
  
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 <WRAP BOX> <WRAP BOX>
-FIXME Please fill in real values for this device, then remove the EXAMPLEs 
- 
 ==== Network interfaces ==== ==== Network interfaces ====
 The default network configuration is: The default network configuration is:
-^ Interface Name   ^ Description                  ^ Default configuration    +^ Interface Name  ^ Description         ^ Default configuration  
-| br-lan           EXAMPLE LAN & WiFi           EXAMPLE 192.168.1.1/24   +| br-lan          | LAN & WiFi          | 192.168.1.1/24         
-vlan0 (eth0.0)   EXAMPLE LAN ports (1 to 4)   EXAMPLE None             +lan(1-4)@eth0   | LAN ports (1 to 4)  | None                   
-vlan1 (eth0.1)   EXAMPLE WAN port             EXAMPLE DHCP             +wan             | WAN port            | DHCP                   
-wl0              EXAMPLE WiFi                 EXAMPLE Disabled         +phy0-ap0        | WiFi 2.4GHz         | Disabled               
 +| phy1-ap0        | WiFi 5GHz           | Disabled               |
 </WRAP> </WRAP>
  
 ==== Switch Ports (for VLANs) ==== ==== Switch Ports (for VLANs) ====
 <WRAP BOX> <WRAP BOX>
-FIXME Please fill in real values for this device, then remove the EXAMPLEs +^ Port            ^ Switch port  
- +| Internet (WAN)               
-Numbers 0-3 are Ports 1-4 as labeled on the unit, number 4 is the Internet (WAN) on the unit, 5 is the internal connection to the router itself. Don't be fooled: Port 1 on the unit is number 3 when configuring VLANs. vlan0 = eth0.0, vlan1 = eth0.1 and so on. +| LAN 1           1            | 
-^ Port             ^ Switch port   +| LAN 2           | 2            
-| Internet (WAN)   EXAMPLE 4     +| LAN 3           3            
-| LAN 1            | EXAMPLE 3     +| LAN 4           4            |
-| LAN 2            EXAMPLE     +
-| LAN 3            EXAMPLE 1     +
-| LAN 4            EXAMPLE 0     |+
  
 </WRAP> </WRAP>
  
 ==== Buttons ==== ==== Buttons ====
--> [[docs:guide-user:hardware:hardware.button]] on howto use and configure the hardware button(s). 
-Here, we merely name the buttons, so we can use them in the above Howto. 
- 
 <WRAP BOX> <WRAP BOX>
-FIXME Please fill in real values for this device, then remove the EXAMPLEs 
- 
 The SNR CPE-ME2-Lite has the following buttons: The SNR CPE-ME2-Lite has the following buttons:
  
-^ BUTTON                       ^ Event   ^ +^ BUTTON               ^ Event   ^ 
-EXAMPLE Reset                |  reset  | +| Reset                |  reset  |
-| EXAMPLE Secure Easy Setup    |   ses   | +
-| EXAMPLE No buttons at all.      -    | +
 </WRAP> </WRAP>
  
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 filter  : Brand=SNR filter  : Brand=SNR
 filter  : Model=CPE-ME2-Lite filter  : Model=CPE-ME2-Lite
-filter  : Versions=+filter  : Versions=rev.B
 ---- ----
  
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 /* =====>>>>> Standard size for photos: add ?400 to the medialink                                */ /* =====>>>>> Standard size for photos: add ?400 to the medialink                                */
 /* When uploading photos, **name them** intelligently. Nobody knows what 20100930_000602.jpg is! */ /* When uploading photos, **name them** intelligently. Nobody knows what 20100930_000602.jpg is! */
-/* e.g. {{:media:yourbrand:yourbrand_yourmodel_front.jpg?400|}}                                  */+/* e.g. {{:media:yourbrand:yourbrand_yourmodel_front.jpg|400|}}                                  */
 /* Thanks, your wiki administration - Oct. 2015 */ /* Thanks, your wiki administration - Oct. 2015 */
  
 //Front://\\ //Front://\\
-**Insert photo of front of the casing**+{{:media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-front.jpg?400}}
  
 //Back://\\ //Back://\\
-**Insert photo of back of the casing**+{{:media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-back.jpg?400}}
  
 //Backside label://\\ //Backside label://\\
-**Insert photo of backside label**+{{:media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-label.jpg?400}}
  
 ==== Opening the case ==== ==== Opening the case ====
Line 295: Line 246:
  
 <WRAP BOX> <WRAP BOX>
-FIXME //Describe what needs to be done to open the device, e.g. remove rubber feet, adhesive labels, screws, ...// +  * To remove the cover and open the device
-  * To remove the cover and open the device, do a/b/c+  - Ordered List Item Unscrew the 4 Phillips screws from the bottom of the device. 
 +  - There are 6 latches around the perimeter between the halves of the case. They need to be pressed by inserting plastic card or other flat object between the halves.
 </WRAP> </WRAP>
 +{{media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-screw-holes.jpg?200}} {{media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-latches.jpg?200}}
  
 //Main PCB://\\ //Main PCB://\\
-**Insert photo of PCB**+{{media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-board-top.jpg?400}} {{media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-board-bottom.jpg?400}} {{media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-board-ports.jpg?400}} 
 + 
 +//Chips on board://\\ 
 +{{media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-spi-chip.jpg?200}} {{media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-wifi2-chip.jpg?200}} 
 + 
 +//LEDS://\\ 
 +{{media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-leds.jpg?400}} 
  
 ==== Serial ==== ==== Serial ====
Line 306: Line 266:
  
 How to connect to the Serial Port of this specific device:\\ How to connect to the Serial Port of this specific device:\\
-**Insert photo of PCB with markings for serial port** +{{:media:snr:cpe-me2-lite:snr-cpe-me2-lite-rev-b-uart.jpg?400}}
- +
-<WRAP BOX> +
-FIXME //Replace EXAMPLE by real values.// +
-</WRAP>+
  
-^ Serial connection parameters\\ for SNR CPE-ME2-Lite @@Version@@ EXAMPLE 115200, 8N1, 3.3V |+^ Serial connection parameters\\ for SNR CPE-ME2-Lite rev.B 57600, 8N1, 3.3V |
  
 ==== JTAG ==== ==== JTAG ====
Line 318: Line 274:
  
 How to connect to the JTAG Port of this specific device:\\ How to connect to the JTAG Port of this specific device:\\
-**Insert photo of PCB with markings for JTAG port**+JTAG not found
  
 ===== Bootloader mods ===== ===== Bootloader mods =====
Line 770: Line 726:
 ==== OpenWrt bootlog ==== ==== OpenWrt bootlog ====
 <WRAP bootlog> <WRAP bootlog>
-<nowiki>COPY HERE THE BOOTLOG ONCE OPENWRT IS INSTALLED AND RUNNING</nowiki> +<nowiki>
-</WRAP>\\+
  
-===== Notes ===== +=================================================================== 
-//Space for additional noteslinks to forum threads or other resources.//+                MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC) 
 +                CPU=500000000 HZ BUS=166666666 HZ 
 +================================================================== 
 +Change MPLL source from XTAL to CR... 
 +do MEMPLL setting.. 
 +MEMPLL Config : 0x11100000 
 +3PLL mode + External loopback 
 +=== XTAL-40Mhz === DDR-1200Mhz === 
 +PLL2 FB_DL: 0xf, 1/0 = 570/454 3D000000 
 +PLL3 FB_DL: 0xf1/0 = 589/435 3D000000 
 +PLL4 FB_DL: 0x17, 1/0 = 540/484 5D000000 
 +do DDR setting..[01F40000] 
 +Apply DDR3 Setting...(use customer AC) 
 +          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120 
 +      -------------------------------------------------------------------------------- 
 +0000:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0001:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0002:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0003:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0004:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0005:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0006:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0007:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0008:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0009:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +000A:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +000B:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +000C:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +000D:   0    0    0    0    0    0    0    0    0    0    0    0    1    1    1    1 
 +000E:   0    0    0    0    0    0    0    1    1    1    1    1    1    1    1    1 
 +000F:   0    1    1    1    1    1    1    1    1    1    1    1    0    0    0    0 
 +0010:   1    1    1    1    1    1    0    0    0    0    0    0    0    0    0    0 
 +0011:   1    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0012:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0013:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0014:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0015:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0016:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0017:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0018:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0019:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001A:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001B:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001C:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001D:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001E:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001F:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +DRAMC_DQSCTL1[0e0]=13000000 
 +DRAMC_DQSGCTL[124]=80000033 
 +rank 0 coarse = 15 
 +rank 0 fine = 48 
 +B:|    0    0    0    0    0    0    0    0    1    1    1    0    0    0    0    0 
 +opt_dle value:9 
 +DRAMC_DDR2CTL[07c]=C287221D 
 +DRAMC_PADCTL4[0e4]=000022B3 
 +DRAMC_DQIDLY1[210]=0E0F0B0F 
 +DRAMC_DQIDLY2[214]=0D0F0D0F 
 +DRAMC_DQIDLY3[218]=0C0E090C 
 +DRAMC_DQIDLY4[21c]=0D0C0E0B 
 +DRAMC_R0DELDLY[018]=0000201F 
 +================================================================== 
 +                RX      DQS perbit delay software calibration 
 +================================================================== 
 +1.0-15 bit dq delay value 
 +================================================================== 
 +bit|      1  2  3  4  5  6  7  8  9 
 +-------------------------------------- 
 +0 |    13 11 14 13 13 11 15 12 11 9 
 +10 |    12 11 9 11 10 9 
 +--------------------------------------
  
-  ...+================================================================== 
 +2.dqs window 
 +x=pass dqs delay value (min~max)center 
 +y=0-7bit DQ of every group 
 +input delay:DQS0 =31 DQS1 = 32 
 +================================================================== 
 +bit     DQS0     bit      DQS1 
 +0  (1~58)29  8  (2~60)31 
 +1  (1~61)31  9  (2~62)32 
 +2  (1~58)29  10  (1~60)30 
 +3  (1~60)30  11  (1~62)31 
 +4  (1~58)29  12  (1~60)30 
 +5  (1~58)29  13  (1~58)29 
 +6  (1~58)29  14  (1~60)30 
 +7  (0~61)30  15  (1~56)28 
 +================================================================== 
 +3.dq delay value last 
 +================================================================== 
 +bit|    0  1  2  3  4  5  6  7  8   
 +-------------------------------------- 
 +0 |    15 11 15 14 15 13 15 13 12 9 
 +10 |    14 12 11 14 12 13 
 +================================================================== 
 +================================================================== 
 +     TX  perbyte calibration 
 +================================================================== 
 +DQS loop = 15, cmp_err_1 = ffff0000 
 +dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1 
 +dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2 
 +DQ loop=15, cmp_err_1 = ffff0000 
 +dqs_perbyte_dly.last_dqdly_pass[0]=15,  finish count=1 
 +dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=2 
 +byte:0, (DQS,DQ)=(8,8) 
 +byte:1, (DQS,DQ)=(8,8) 
 +DRAMC_DQODLY1[200]=88888888 
 +DRAMC_DQODLY2[204]=88888888 
 +20,data:88 
 +[EMI] DRAMC calibration passed
  
 +===================================================================
 +                MT7621   stage1 code done
 +                CPU=500000000 HZ BUS=166666666 HZ
 +===================================================================
 +
 +
 +U-Boot 1.1.3 (Jun 25 2020 - 13:46:13)
 +
 +Board: MediaTek APSoC DRAM: 128 MB
 +
 +Config XHCI 40M PLL
 +MediaTek SPI flash driver, SPI clock: 31MHz
 +spi device id: 1c 70 18 1c
 +find flash: EN25QH128A
 +*** Warning - bad CRC, using default environment
 +
 +============================================
 +MediaTek U-Boot Version: 5.0.1.0-6
 +--------------------------------------------
 +ASIC MT7621A DualCore (MAC to MT7530 Mode)
 +DRAM_CONF_FROM: Auto-Detection
 +DRAM_TYPE: DDR3
 +DRAM bus: 16 bit
 +Xtal Mode=3 OCP Ratio=1/3
 +Flash component: SPI Flash
 +Date:Jun 25 2020  Time:13:46:13
 +============================================
 +icache: sets:256, ways:4, linesz:32, total:32768
 +dcache: sets:256, ways:4, linesz:32, total:32768
 +
 + #### The CPU freq = 880 MHZ ####
 + estimate memory size = 128 Mbytes
 +
 + Reset MT7530
 +set LAN/WAN WLLLL
 +
 +Please choose the operation:
 +   0: Load system code then write to Flash via Serial.
 +   1: Load system code to SDRAM via TFTP.
 +   2: Load system code then write to Flash via TFTP.
 +   3: Boot system code via Flash (default).
 +   4: Enter boot command line interface.
 +   7: Load U-Boot code then write to Flash via Serial.
 +   9: Load U-Boot code then write to Flash via TFTP.                                                                                      0
 +
 +
 +3: System Boot system code via Flash.
 +## Checking image at bc050000 ...
 +   Image Name:   SNR-CPE-ME2-Lite
 +   Image Type:   MIPS Linux Kernel Image (uncompressed)
 +   Data Size:    2811990 Bytes =  2.7 MB
 +   Load Address: 80001000
 +   Entry Point:  80001000
 +   Verifying Checksum ... OK
 +OK
 +No initrd
 +## Transferring control to Linux (at address 80001000) ...
 +## Giving linux memsize in MB, 128
 +
 +Starting kernel ...
 +
 +
 +
 +OpenWrt kernel loader for MIPS based SoC
 +Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
 +Decompressing kernel... done!
 +Starting kernel at 80001000...
 +
 +[    0.000000] Linux version 5.15.167 (builder@buildhost) (mipsel-openwrt-linux-musl-gcc (OpenWrt GCC 12.3.0 r24106-10cc5fcd00) 12.3.0, GNU ld (GNU Binutils) 2.40.0) #0 SMP Mon Sep 23 12:34:46 2024
 +[    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3
 +[    0.000000] printk: bootconsole [early0] enabled
 +[    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
 +[    0.000000] MIPS: machine is SNR-CPE-ME2-Lite
 +[    0.000000] Initrd not found or empty - disabling initrd
 +[    0.000000] VPE topology {2,2} total 4
 +[    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
 +[    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
 +[    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
 +[    0.000000] Zone ranges:
 +[    0.000000]   Normal   [mem 0x0000000000000000-0x0000000007ffffff]
 +[    0.000000] Movable zone start for each node
 +[    0.000000] Early memory node ranges
 +[    0.000000]   node   0: [mem 0x0000000000000000-0x0000000007ffffff]
 +[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
 +[    0.000000] percpu: Embedded 12 pages/cpu s17808 r8192 d23152 u49152
 +[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32480
 +[    0.000000] Kernel command line: console=ttyS0,57600 rootfstype=squashfs,jffs2
 +[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
 +[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
 +[    0.000000] Writing ErrCtl register=00011a42
 +[    0.000000] Readback ErrCtl register=00011a42
 +[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
 +[    0.000000] Memory: 119220K/131072K available (7323K kernel code, 629K rwdata, 884K rodata, 1264K init, 225K bss, 11852K reserved, 0K cma-reserved)
 +[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
 +[    0.000000] rcu: Hierarchical RCU implementation.
 +[    0.000000]  Tracing variant of Tasks RCU enabled.
 +[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
 +[    0.000000] NR_IRQS: 256
 +[    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcaf478abb4, max_idle_ns: 440795247997 ns
 +[    0.000004] sched_clock: 64 bits at 880MHz, resolution 1ns, wraps every 4398046511103ns
 +[    0.016015] Calibrating delay loop... 586.13 BogoMIPS (lpj=2930688)
 +[    0.088318] pid_max: default: 32768 minimum: 301
 +[    0.098270] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
 +[    0.112686] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
 +[    0.131872] rcu: Hierarchical SRCU implementation.
 +[    0.142081] smp: Bringing up secondary CPUs ...
 +[    0.151852] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
 +[    0.151876] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
 +[    0.151891] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
 +[    0.151935] CPU1 revision is: 0001992f (MIPS 1004Kc)
 +[    0.211621] Synchronize counters for CPU 1: done.
 +[    0.273814] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
 +[    0.273834] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
 +[    0.273845] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
 +[    0.273872] CPU2 revision is: 0001992f (MIPS 1004Kc)
 +[    0.332791] Synchronize counters for CPU 2: done.
 +[    0.393166] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
 +[    0.393186] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
 +[    0.393197] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
 +[    0.393228] CPU3 revision is: 0001992f (MIPS 1004Kc)
 +[    0.452365] Synchronize counters for CPU 3: done.
 +[    0.511961] smp: Brought up 1 node, 4 CPUs
 +[    0.525040] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
 +[    0.544530] futex hash table entries: 1024 (order: 3, 32768 bytes, linear)
 +[    0.558435] pinctrl core: initialized pinctrl subsystem
 +[    0.570306] NET: Registered PF_NETLINK/PF_ROUTE protocol family
 +[    0.582772] thermal_sys: Registered thermal governor 'step_wise'
 +[    0.613982] clocksource: Switched to clocksource GIC
 +[    0.625264] NET: Registered PF_INET protocol family
 +[    0.635042] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear)
 +[    0.650258] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
 +[    0.666808] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
 +[    0.682164] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear)
 +[    0.697372] TCP bind hash table entries: 1024 (order: 1, 8192 bytes, linear)
 +[    0.711376] TCP: Hash tables configured (established 1024 bind 1024)
 +[    0.724133] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
 +[    0.737048] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
 +[    0.751229] NET: Registered PF_UNIX/PF_LOCAL protocol family
 +[    0.762430] PCI: CLS 0 bytes, default 32
 +[    0.772885] workingset: timestamp_bits=14 max_order=15 bucket_order=1
 +[    0.790995] squashfs: version 4.0 (2009/01/31) Phillip Lougher
 +[    0.802572] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
 +[    0.823472] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251)
 +[    0.841929] mt7621_gpio 1e000600.gpio: registering 32 gpios
 +[    0.853472] mt7621_gpio 1e000600.gpio: registering 32 gpios
 +[    0.864897] mt7621_gpio 1e000600.gpio: registering 32 gpios
 +[    0.876439] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges:
 +[    0.889712] mt7621-pci 1e140000.pcie:   No bus range found for /pcie@1e140000, using [bus 00-ff]
 +[    0.907191] mt7621-pci 1e140000.pcie:      MEM 0x0060000000..0x006fffffff -> 0x0060000000
 +[    0.923403] mt7621-pci 1e140000.pcie:       IO 0x001e160000..0x001e16ffff -> 0x0000000000
 +[    1.293983] mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
 +[    1.307755] mt7621-pci 1e140000.pcie: PCIE0 enabled
 +[    1.317407] mt7621-pci 1e140000.pcie: PCIE1 enabled
 +[    1.327105] PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
 +[    1.341292] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
 +[    1.353818] pci_bus 0000:00: root bus resource [bus 00-ff]
 +[    1.364696] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
 +[    1.378340] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
 +[    1.390656] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400
 +[    1.402546] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x7fffffff]
 +[    1.414984] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
 +[    1.427527] pci 0000:00:00.0: supports D1
 +[    1.435375] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
 +[    1.447553] pci 0000:00:01.0: [0e8d:0801] type 01 class 0x060400
 +[    1.459484] pci 0000:00:01.0: reg 0x10: [mem 0x00000000-0x7fffffff]
 +[    1.471879] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x0000ffff]
 +[    1.484404] pci 0000:00:01.0: supports D1
 +[    1.492230] pci 0000:00:01.0: PME# supported from D0 D1 D3hot
 +[    1.505558] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
 +[    1.521417] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
 +[    1.537544] pci 0000:01:00.0: [14c3:7603] type 00 class 0x028000
 +[    1.549430] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
 +[    1.561949] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
 +[    1.575310] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
 +[    1.585625] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff]
 +[    1.597691] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff]
 +[    1.611189] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff pref]
 +[    1.625542] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
 +[    1.638938] pci 0000:02:00.0: [14c3:7663] type 00 class 0x000280
 +[    1.650814] pci 0000:02:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
 +[    1.665136] pci 0000:02:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
 +[    1.679467] pci 0000:02:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
 +[    1.693907] pci 0000:02:00.0: supports D1 D2
 +[    1.702271] pci 0000:02:00.0: PME# supported from D0 D1 D2 D3hot D3cold
 +[    1.715433] pci 0000:02:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x1 link at 0000:00:01.0 (capable of 4.000 Gb/s with 5.0 GT/s PCIe x1 link)
 +[    1.746269] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
 +[    1.756580] pci 0000:00:01.0:   bridge window [io  0x0000-0x0fff]
 +[    1.768649] pci 0000:00:01.0:   bridge window [mem 0x00000000-0x000fffff]
 +[    1.782134] pci 0000:00:01.0:   bridge window [mem 0x00000000-0x000fffff pref]
 +[    1.796484] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
 +[    1.809665] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
 +[    1.822735] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
 +[    1.836563] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
 +[    1.849696] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
 +[    1.863517] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
 +[    1.877008] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref]
 +[    1.891344] pci 0000:00:01.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
 +[    1.904816] pci 0000:00:01.0: BAR 9: assigned [mem 0x60300000-0x604fffff pref]
 +[    1.919172] pci 0000:00:00.0: BAR 1: assigned [mem 0x60500000-0x6050ffff]
 +[    1.932641] pci 0000:00:01.0: BAR 1: assigned [mem 0x60510000-0x6051ffff]
 +[    1.946129] pci 0000:00:00.0: BAR 7: assigned [io  0x0000-0x0fff]
 +[    1.958218] pci 0000:00:01.0: BAR 7: assigned [io  0x1000-0x1fff]
 +[    1.970316] pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x600fffff]
 +[    1.983796] pci 0000:00:00.0: PCI bridge to [bus 01]
 +[    1.993634] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff]
 +[    2.005743] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
 +[    2.019215] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref]
 +[    2.033557] pci 0000:02:00.0: BAR 0: assigned [mem 0x60300000-0x603fffff 64bit pref]
 +[    2.048954] pci 0000:02:00.0: BAR 2: assigned [mem 0x60400000-0x60403fff 64bit pref]
 +[    2.064334] pci 0000:02:00.0: BAR 4: assigned [mem 0x60404000-0x60404fff 64bit pref]
 +[    2.079706] pci 0000:00:01.0: PCI bridge to [bus 02]
 +[    2.089537] pci 0000:00:01.0:   bridge window [io  0x1000-0x1fff]
 +[    2.101641] pci 0000:00:01.0:   bridge window [mem 0x60200000-0x602fffff]
 +[    2.115112] pci 0000:00:01.0:   bridge window [mem 0x60300000-0x604fffff pref]
 +[    2.132068] Serial: 8250/16550 driver, 16 ports, IRQ sharing enabled
 +[    2.149284] printk: console [ttyS0] disabled
 +[    2.157822] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 19, base_baud = 3125000) is a 16550A
 +[    2.175765] printk: console [ttyS0] enabled
 +[    2.175765] printk: console [ttyS0] enabled
 +[    2.192308] printk: bootconsole [early0] disabled
 +[    2.192308] printk: bootconsole [early0] disabled
 +[    2.214990] spi-mt7621 1e000b00.spi: sys_freq: 220000000
 +[    2.226934] spi-nor spi0.0: en25qh128 (16384 Kbytes)
 +[    2.236998] 4 fixed-partitions partitions found on MTD device spi0.0
 +[    2.249705] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions
 +[    2.264315] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions
 +[    2.279412] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions
 +[    2.294094] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions
 +[    2.308958] Creating 4 MTD partitions on "spi0.0":
 +[    2.318538] 0x000000000000-0x000000030000 : "u-boot"
 +[    2.329585] 0x000000030000-0x000000040000 : "config"
 +[    2.340534] 0x000000040000-0x000000050000 : "factory"
 +[    2.351638] 0x000000050000-0x000001000000 : "firmware"
 +[    2.363205] 2 uimage-fw partitions found on MTD device firmware
 +[    2.375075] Creating 2 MTD partitions on "firmware":
 +[    2.384998] 0x000000000000-0x0000002ae896 : "kernel"
 +[    2.394895] mtd: partition "kernel" doesn't end on an erase/write block -- force read-only
 +[    2.412464] 0x0000002ae896-0x000000fb0000 : "rootfs"
 +[    2.422415] mtd: partition "rootfs" doesn't start on an erase/write block boundary -- force read-only
 +[    2.441576] mtd: setting mtd5 (rootfs) as root device
 +[    2.451808] 1 squashfs-split partitions found on MTD device rootfs
 +[    2.464136] 0x0000006a0000-0x000000fb0000 : "rootfs_data"
 +[    2.617021] mt7530-mdio mdio-bus:1f: MT7530 adapts as multi-chip module
 +[    2.639264] mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 23
 +[    2.659735] mtk_soc_eth 1e100000.ethernet wan: mediatek frame engine at 0xbe100000, irq 23
 +[    2.679110] i2c_dev: i2c /dev entries driver
 +[    2.690678] NET: Registered PF_INET6 protocol family
 +[    2.703060] Segment Routing with IPv6
 +[    2.710482] In-situ OAM (IOAM) with IPv6
 +[    2.718456] NET: Registered PF_PACKET protocol family
 +[    2.728656] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
 +[    2.754947] 8021q: 802.1Q VLAN Support v1.8
 +[    2.769332] mt7530-mdio mdio-bus:1f: MT7530 adapts as multi-chip module
 +[    2.805989] mt7530-mdio mdio-bus:1f: configuring for fixed/rgmii link mode
 +[    2.820656] mt7530-mdio mdio-bus:1f: Link is Up - 1Gbps/Full - flow control rx/tx
 +[    2.825037] mt7530-mdio mdio-bus:1f lan1 (uninitialized): PHY [mt7530-0:01] driver [MediaTek MT7530 PHY] (irq=25)
 +[    2.858889] mt7530-mdio mdio-bus:1f lan2 (uninitialized): PHY [mt7530-0:02] driver [MediaTek MT7530 PHY] (irq=26)
 +[    2.881913] mt7530-mdio mdio-bus:1f lan3 (uninitialized): PHY [mt7530-0:03] driver [MediaTek MT7530 PHY] (irq=27)
 +[    2.905071] mt7530-mdio mdio-bus:1f lan4 (uninitialized): PHY [mt7530-0:04] driver [MediaTek MT7530 PHY] (irq=28)
 +[    2.927508] DSA: tree 0 setup
 +[    2.934927] clk: Disabling unused clocks
 +[    2.948253] VFS: Mounted root (squashfs filesystem) readonly on device 31:5.
 +[    2.966516] Freeing unused kernel image (initmem) memory: 1264K
 +[    2.978390] This architecture does not have kernel memory protection.
 +[    2.991246] Run /sbin/init as init process
 +[    3.421492] init: Console is alive
 +[    3.428859] init: - watchdog -
 +[    4.118159] kmodloader: loading kernel modules from /etc/modules-boot.d/*
 +[    4.179112] kmodloader: done loading kernel modules from /etc/modules-boot.d/*
 +[    4.204320] init: - preinit -
 +[    5.005593] random: jshn: uninitialized urandom read (4 bytes read)
 +[    5.129842] random: jshn: uninitialized urandom read (4 bytes read)
 +[    5.175246] random: jshn: uninitialized urandom read (4 bytes read)
 +[    5.465284] mtk_soc_eth 1e100000.ethernet eth0: configuring for fixed/rgmii link mode
 +[    5.485851] mtk_soc_eth 1e100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
 +[    5.486267] mt7530-mdio mdio-bus:1f lan1: configuring for phy/gmii link mode
 +[    5.517278] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
 +Press the [f] key and hit [enter] to enter failsafe mode
 +Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level
 +[    7.726247] jffs2: notice: (435) jffs2_build_xattr_subsystem: complete building xattr subsystem, 19 of xdatum (7 unchecked, 10 orphan) and 22 of xref (2 dead, 9 orphan) found.
 +[    7.759623] mount_root: switching to jffs2 overlay
 +[    7.779007] overlayfs: upper fs does not support tmpfile.
 +[    7.800876] urandom-seed: Seeding with /etc/urandom.seed
 +[    7.912457] procd: - early -
 +[    7.918542] procd: - watchdog -
 +[    8.523182] procd: - watchdog -
 +[    8.530455] procd: - ubus -
 +[    8.596536] random: ubusd: uninitialized urandom read (4 bytes read)
 +[    8.612089] random: ubusd: uninitialized urandom read (4 bytes read)
 +[    8.710726] random: ubusd: uninitialized urandom read (4 bytes read)
 +[    8.733230] procd: - init -
 +Please press Enter to activate this console.
 +[    9.291993] kmodloader: loading kernel modules from /etc/modules.d/*
 +[    9.527067] Loading modules backported from Linux version v6.1.110-0-g5f55cad62cc9d
 +[    9.542363] Backport generated by backports.git v6.1.110-1-0-g965f73fc
 +[    9.750124] pci 0000:00:00.0: enabling device (0000 -> 0003)
 +[    9.761534] mt7603e 0000:01:00.0: enabling device (0000 -> 0002)
 +[    9.773725] mt7603e 0000:01:00.0: ASIC revision: 76030010
 +[    9.792166] mt7603e 0000:01:00.0: Firmware Version: ap_pcie
 +[    9.803377] mt7603e 0000:01:00.0: Build Time: 20160107100755
 +[    9.854015] mt7603e 0000:01:00.0: firmware init done
 +[   10.031837] mt7603e 0000:01:00.0: registering led 'mt76-phy0'
 +[   10.096535] pci 0000:00:01.0: enabling device (0000 -> 0003)
 +[   10.107892] mt7615e 0000:02:00.0: enabling device (0000 -> 0002)
 +[   10.131316] mt7615e 0000:02:00.0: registering led 'mt76-phy1'
 +[   10.238346] PPP generic driver version 2.4.2
 +[   10.248399] NET: Registered PF_PPPOX protocol family
 +[   10.270656] kmodloader: done loading kernel modules from /etc/modules.d/*
 +[   10.356747] random: jshn: uninitialized urandom read (4 bytes read)
 +[   10.647705] urngd: v1.0.2 started.
 +[   11.028292] random: jshn: uninitialized urandom read (4 bytes read)
 +[   11.052409] random: ubusd: uninitialized urandom read (4 bytes read)
 +[   11.507083] random: jshn: uninitialized urandom read (4 bytes read)
 +[   11.768252] random: crng init done
 +[   11.775274] random: 42 urandom warning(s) missed due to ratelimiting
 +[   12.270617] mt7615e 0000:02:00.0: mediatek/mt7663pr2h.bin not found, switching to mediatek/mt7663pr2h_rebb.bin
 +[   12.455161] mt7615e 0000:02:00.0: HW/SW Version: 0x65322d31, Build Time: 2009041715da1a1
 +[   12.455161]
 +[   12.624130] mt7615e 0000:02:00.0: N9 Firmware Version: 7663mp1827, Build Time: 20200904171623
 +[   12.641281] mt7615e 0000:02:00.0: Region number: 0x3
 +[   12.651349] mt7615e 0000:02:00.0: Parsing tailer Region: 0
 +[   12.665354] mt7615e 0000:02:00.0: Region 0, override_addr = 0x00112c00
 +[   12.678479] mt7615e 0000:02:00.0: Parsing tailer Region: 1
 +[   12.690496] mt7615e 0000:02:00.0: Parsing tailer Region: 2
 +[   12.702043] mt7615e 0000:02:00.0: override_addr = 0x00112c00, option = 3
 +[   18.474632] mtk_soc_eth 1e100000.ethernet eth0: Link is Down
 +[   18.514563] mtk_soc_eth 1e100000.ethernet eth0: configuring for fixed/rgmii link mode
 +[   18.530594] mtk_soc_eth 1e100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
 +[   18.537637] mt7530-mdio mdio-bus:1f lan1: configuring for phy/gmii link mode
 +[   18.564927] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
 +[   18.578795] br-lan: port 1(lan1) entered blocking state
 +[   18.589338] br-lan: port 1(lan1) entered disabled state
 +[   18.602345] device lan1 entered promiscuous mode
 +[   18.611704] device eth0 entered promiscuous mode
 +[   18.652202] mt7530-mdio mdio-bus:1f lan2: configuring for phy/gmii link mode
 +[   18.668959] br-lan: port 2(lan2) entered blocking state
 +[   18.679496] br-lan: port 2(lan2) entered disabled state
 +[   18.692425] device lan2 entered promiscuous mode
 +[   18.716580] mt7530-mdio mdio-bus:1f lan3: configuring for phy/gmii link mode
 +[   18.732915] br-lan: port 3(lan3) entered blocking state
 +[   18.743477] br-lan: port 3(lan3) entered disabled state
 +[   18.756995] device lan3 entered promiscuous mode
 +[   18.779570] mt7530-mdio mdio-bus:1f lan4: configuring for phy/gmii link mode
 +[   18.796386] br-lan: port 4(lan4) entered blocking state
 +[   18.806926] br-lan: port 4(lan4) entered disabled state
 +[   18.821185] device lan4 entered promiscuous mode
 +[   18.853090] mtk_soc_eth 1e100000.ethernet wan: PHY [mdio-bus:00] driver [MediaTek MT7530 PHY] (irq=POLL)
 +[   18.872092] mtk_soc_eth 1e100000.ethernet wan: configuring for phy/rgmii link mode
 +[   21.334097] mt7530-mdio mdio-bus:1f lan1: Link is Up - 1Gbps/Full - flow control rx/tx
 +[   21.334180] br-lan: port 1(lan1) entered blocking state
 +[   21.360347] br-lan: port 1(lan1) entered forwarding state
 +[   21.372099] IPv6: ADDRCONF(NETDEV_CHANGE): br-lan: link becomes ready
 +</nowiki>
 +</WRAP>\\
 +
 +===== Notes =====
 +  * [[commit>?p=openwrt/openwrt.git;a=commit;h=a664d39c5bb4a77ffc90a6fdfdca3606292b650d|Commit]]
 +  * [[https://snr.global/Wi-Fi-5/789-SNR-CPE-ME2-Lite-rev-B.html|Product page]]
 ===== Tags ===== ===== Tags =====
-<WRAP BOX> 
-FIXME //Add tags below, then remove this fixme.// 
-</WRAP> 
  
-[[meta:tags|How to add tags]] +{{tag>U-boot 2core MT7621 128RAM 16Flash GigabitEthernet wlan 802.11ac 4Ant 5Port SPI Serial 1button "12v powered"}} 
-{{tag>EXAMPLETAG}}+
  • Last modified: 2024/12/18 15:02
  • by frollic