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| toh:snr:cpe-me2-lite [2024/12/10 10:07] – Created from the form at meta:create_new_device_page wertwert4pda | toh:snr:cpe-me2-lite [2024/12/11 14:41] – [OEM easy installation] wertwert4pda | ||
|---|---|---|---|
| Line 5: | Line 5: | ||
| /* USE https:// | /* USE https:// | ||
| - | {{page> | + | Wi-Fi Mesh router AC1200, IEEE 802.11 a/b/g/n/ac 1GE WAN 4 GE LAN. IPv6, IGMP, TR-069 |
| - | + | ||
| - | //Write a short, relevant description of the device. Include | + | |
| - | + | ||
| - | <WRAP BOX> | + | |
| - | FIXME Any text with a light background (like this one) provides instructions for creating the Details Page. When you have filled in correct/ | + | |
| - | </ | + | |
| /*****/ | /*****/ | ||
| Line 17: | Line 11: | ||
| /*****/ | /*****/ | ||
| - | {{media:example:genericrouter1.png?200|Generic | + | {{media:snr:cpe-me2-lite: |
| - | + | {{media: | |
| - | <WRAP BOX> | + | |
| - | FIXME | + | |
| - | ===== Getting started with a new Device Page ===== | + | |
| - | | + | |
| - | | + | |
| - | | + | |
| - | + | ||
| - | ===== Keep the articles modular ===== | + | |
| - | * Please include only model specific information, | + | |
| - | * If you have no time to write certain stuff, link to [[docs: | + | |
| - | * [[docs: | + | |
| - | * DO NOT provide a complete howto here! Instead //groom// the [[docs: | + | |
| - | </ | + | |
| ===== Supported Versions ===== | ===== Supported Versions ===== | ||
| - | |||
| - | <WRAP BOX> | ||
| - | FIXME | ||
| - | - The tables below are automatically generated, **once the correct filters for Brand and Model are set.** | ||
| - | - If the tables below show information for ''< | ||
| - | - If the tables below contain " | ||
| - | - the dataentry page for SNR CPE-ME2-Lite | ||
| - | - filters are not set correctly. Most common reason for " | ||
| - | - If the tables still contain " | ||
| - | </ | ||
| - | |||
| <!-- ToH: { | <!-- ToH: { | ||
| " | " | ||
| " | " | ||
| " | " | ||
| + | " | ||
| " | " | ||
| - | " | + | " |
| } --> | } --> | ||
| /* If no unsupported functions known, comment out the following datatable or delete it. */ | /* If no unsupported functions known, comment out the following datatable or delete it. */ | ||
| - | <!-- ToH: { | + | /* <!-- ToH: { |
| " | " | ||
| " | " | ||
| Line 60: | Line 31: | ||
| " | " | ||
| " | " | ||
| - | } --> | + | } --> |
| ===== Experimental Versions ===== | ===== Experimental Versions ===== | ||
| Line 78: | Line 49: | ||
| " | " | ||
| " | " | ||
| + | " | ||
| " | " | ||
| - | " | + | " |
| } --> | } --> | ||
| Line 85: | Line 57: | ||
| ===== Installation ===== | ===== Installation ===== | ||
| /* stable release */ | /* stable release */ | ||
| - | /* uncomment once stable release is available | + | /* uncomment once stable release is available |
| <!-- ToH: { | <!-- ToH: { | ||
| " | " | ||
| " | " | ||
| " | " | ||
| + | " | ||
| " | " | ||
| - | " | + | " |
| } --> | } --> | ||
| - | */ | + | |
| /* snapshot */ | /* snapshot */ | ||
| - | /* delete once stable release is available | + | /* delete once stable release is available |
| <!-- ToH: { | <!-- ToH: { | ||
| " | " | ||
| Line 103: | Line 76: | ||
| " | " | ||
| " | " | ||
| - | " | + | " |
| } --> | } --> | ||
| + | */ | ||
| -> [[docs: | -> [[docs: | ||
| - | FIXME Please add the installation procedure here. | + | |
| ==== Flash Layout ==== | ==== Flash Layout ==== | ||
| <WRAP BOX> | <WRAP BOX> | ||
| - | FIXME //[[:docs:techref:flash.layout# | + | spi-nor spi0.0: en25qh128 (16384 Kbytes) |
| - | + | < | |
| - | Please check out the article [[docs:techref:flash.layout|Flash layout]]. It contains examples and explanations that describe how to document the flash layout. | + | cat /proc/mtd |
| + | dev: | ||
| + | mtd0: 00030000 00010000 " | ||
| + | mtd1: 00010000 00010000 " | ||
| + | mtd2: 00010000 00010000 " | ||
| + | mtd3: 00fb0000 00010000 " | ||
| + | mtd4: 00320767 00010000 " | ||
| + | mtd5: 00c8f899 00010000 " | ||
| + | mtd6: 00840000 00010000 " | ||
| + | </ | ||
| </ | </ | ||
| Line 121: | Line 103: | ||
| <WRAP BOX> | <WRAP BOX> | ||
| - | FIXME //The instructions below are for Broadcom devices and only serve as an example.// | ||
| - | **//Remove / modify them if they do not apply to this particular device!//** | ||
| - | |||
| This section deals with | This section deals with | ||
| * How you install OpenWrt from a device freshly opened | * How you install OpenWrt from a device freshly opened | ||
| Line 129: | Line 108: | ||
| **Note:** Reset router to factory defaults if it has been previously configured. | **Note:** Reset router to factory defaults if it has been previously configured. | ||
| - | | + | |
| - | * Upload | + | **Flash instruction via WEB (old factory firmware 1.10.x)** |
| - | | + | 1. Boot SNR-CPE-ME2-Lite normally with " |
| - | * Telnet to 192.168.1.1 and set a root password, or browse | + | 2. Access |
| + | 3. Select the OpenWrt sysupgrade image in " | ||
| + | | ||
| + | |||
| + | **Note: For new factory firmware (EasyWRT 2.6.x) need downgrade | ||
| + | |||
| </ | </ | ||
| Line 143: | Line 127: | ||
| <WRAP BOX> | <WRAP BOX> | ||
| - | FIXME Enter values for " | + | ^ Bootloader tftp server IPv4 address |
| - | + | ^ Bootloader MAC address (special) | |
| - | ^ Bootloader tftp server IPv4 address | + | ^ Firmware tftp image | [[: |
| - | ^ Bootloader MAC address (special) | + | ^ TFTP transfer window |
| - | ^ Firmware tftp image | [[: | + | ^ TFTP window start | approximately |
| - | ^ TFTP transfer window | + | ^ TFTP client required IP address |
| - | ^ TFTP window start | approximately | + | |
| - | ^ TFTP client required IP address | + | |
| </ | </ | ||
| Line 158: | Line 140: | ||
| <WRAP BOX> | <WRAP BOX> | ||
| - | |||
| - | FIXME These are generic instructions. Update with your router' | ||
| ==== LuCI Web Upgrade Process ==== | ==== LuCI Web Upgrade Process ==== | ||
| Line 170: | Line 150: | ||
| If you don't have a GUI (LuCI) available, you can alternatively upgrade via the command line. | If you don't have a GUI (LuCI) available, you can alternatively upgrade via the command line. | ||
| - | There are two command line methods for upgrading: | ||
| - | |||
| - | * '' | ||
| - | * '' | ||
| Note: It is important that you put the firmware image into the ramdisk (/tmp) before you start flashing. | Note: It is important that you put the firmware image into the ramdisk (/tmp) before you start flashing. | ||
| Line 185: | Line 161: | ||
| wget http:// | wget http:// | ||
| sysupgrade / | sysupgrade / | ||
| - | </ | ||
| - | |||
| - | === mtd === | ||
| - | |||
| - | If '' | ||
| - | |||
| - | * Login as root via SSH on 192.168.1.1, | ||
| - | |||
| - | < | ||
| - | cd /tmp | ||
| - | wget http:// | ||
| - | mtd write / | ||
| </ | </ | ||
| Line 214: | Line 178: | ||
| <WRAP BOX> | <WRAP BOX> | ||
| - | FIXME Please fill in real values for this device, then remove the EXAMPLEs | ||
| - | |||
| ==== Network interfaces ==== | ==== Network interfaces ==== | ||
| The default network configuration is: | The default network configuration is: | ||
| - | ^ Interface Name | + | ^ Interface Name ^ Description |
| - | | br-lan | + | | br-lan |
| - | | vlan0 (eth0.0) | + | | lan(1-4)@eth0 | LAN ports (1 to 4) | None |
| - | | vlan1 (eth0.1) | + | | wan | WAN port | DHCP |
| - | | wl0 | + | | phy0-ap0 |
| + | | phy1-ap0 | ||
| </ | </ | ||
| ==== Switch Ports (for VLANs) ==== | ==== Switch Ports (for VLANs) ==== | ||
| <WRAP BOX> | <WRAP BOX> | ||
| - | FIXME Please fill in real values for this device, then remove the EXAMPLEs | + | ^ Port ^ Switch port ^ |
| - | + | | Internet (WAN) | | | |
| - | Numbers 0-3 are Ports 1-4 as labeled on the unit, number 4 is the Internet (WAN) on the unit, 5 is the internal connection to the router itself. Don't be fooled: Port 1 on the unit is number 3 when configuring VLANs. vlan0 = eth0.0, vlan1 = eth0.1 and so on. | + | | LAN 1 |
| - | ^ Port | + | | LAN 2 |
| - | | Internet (WAN) | + | | LAN 3 |
| - | | LAN 1 | + | | LAN 4 |
| - | | LAN 2 | EXAMPLE | + | |
| - | | LAN 3 | EXAMPLE 1 | | + | |
| - | | LAN 4 | EXAMPLE 0 | | + | |
| </ | </ | ||
| ==== Buttons ==== | ==== Buttons ==== | ||
| - | -> [[docs: | ||
| - | Here, we merely name the buttons, so we can use them in the above Howto. | ||
| - | |||
| <WRAP BOX> | <WRAP BOX> | ||
| - | FIXME Please fill in real values for this device, then remove the EXAMPLEs | ||
| - | |||
| The SNR CPE-ME2-Lite has the following buttons: | The SNR CPE-ME2-Lite has the following buttons: | ||
| - | ^ BUTTON | + | ^ BUTTON |
| - | | EXAMPLE | + | | Reset | reset | |
| - | | EXAMPLE Secure Easy Setup | | + | |
| - | | EXAMPLE No buttons at all. | + | |
| </ | </ | ||
| Line 272: | Line 223: | ||
| filter | filter | ||
| filter | filter | ||
| - | filter | + | filter |
| ---- | ---- | ||
| Line 278: | Line 229: | ||
| /* =====>>>>> | /* =====>>>>> | ||
| /* When uploading photos, **name them** intelligently. Nobody knows what 20100930_000602.jpg is! */ | /* When uploading photos, **name them** intelligently. Nobody knows what 20100930_000602.jpg is! */ | ||
| - | /* e.g. {{: | + | /* e.g. {{: |
| /* Thanks, your wiki administration - Oct. 2015 */ | /* Thanks, your wiki administration - Oct. 2015 */ | ||
| // | // | ||
| - | **Insert photo of front of the casing** | + | {{: |
| //Back://\\ | //Back://\\ | ||
| - | **Insert photo of back of the casing** | + | {{: |
| //Backside label://\\ | //Backside label://\\ | ||
| - | **Insert photo of backside | + | {{: |
| ==== Opening the case ==== | ==== Opening the case ==== | ||
| Line 295: | Line 246: | ||
| <WRAP BOX> | <WRAP BOX> | ||
| - | FIXME //Describe what needs to be done to open the device, e.g. remove rubber feet, adhesive labels, screws, ...// | + | |
| - | | + | - Ordered List Item Unscrew the 4 Phillips screws from the bottom of the device. |
| + | - There are 6 latches around the perimeter between the halves of the case. They need to be pressed by inserting | ||
| </ | </ | ||
| + | {{media: | ||
| //Main PCB://\\ | //Main PCB://\\ | ||
| - | **Insert photo of PCB** | + | {{media: |
| + | |||
| + | //Chips on board:// | ||
| + | {{media: | ||
| + | |||
| + | // | ||
| + | {{media: | ||
| ==== Serial ==== | ==== Serial ==== | ||
| Line 306: | Line 266: | ||
| How to connect to the Serial Port of this specific device:\\ | How to connect to the Serial Port of this specific device:\\ | ||
| - | **Insert photo of PCB with markings for serial port** | + | {{: |
| - | <WRAP BOX> | + | ^ Serial connection parameters\\ for SNR CPE-ME2-Lite |
| - | FIXME //Replace EXAMPLE by real values.// | + | |
| - | </ | + | |
| - | + | ||
| - | ^ Serial connection parameters\\ for SNR CPE-ME2-Lite | + | |
| ==== JTAG ==== | ==== JTAG ==== | ||
| Line 318: | Line 274: | ||
| How to connect to the JTAG Port of this specific device:\\ | How to connect to the JTAG Port of this specific device:\\ | ||
| - | **Insert photo of PCB with markings for JTAG port** | + | JTAG not found |
| ===== Bootloader mods ===== | ===== Bootloader mods ===== | ||
| Line 331: | Line 287: | ||
| ==== OEM bootlog ==== | ==== OEM bootlog ==== | ||
| <WRAP bootlog> | <WRAP bootlog> | ||
| - | < | + | < |
| + | =================================================================== | ||
| + | MT7621 | ||
| + | CPU=500000000 HZ BUS=166666666 HZ | ||
| + | ================================================================== | ||
| + | Change MPLL source from XTAL to CR... | ||
| + | do MEMPLL setting.. | ||
| + | MEMPLL Config : 0x11100000 | ||
| + | 3PLL mode + External loopback | ||
| + | === XTAL-40Mhz === DDR-1200Mhz === | ||
| + | PLL2 FB_DL: 0xf, 1/0 = 584/440 3D000000 | ||
| + | PLL3 FB_DL: 0xf, 1/0 = 649/375 3D000000 | ||
| + | PLL4 FB_DL: 0x17, 1/0 = 652/372 5D000000 | ||
| + | do DDR setting..[01F40000] | ||
| + | Apply DDR3 Setting...(use customer AC) | ||
| + | 0 8 | ||
| + | -------------------------------------------------------------------------------- | ||
| + | 0000: | ||
| + | 0001: | ||
| + | 0002: | ||
| + | 0003: | ||
| + | 0004: | ||
| + | 0005: | ||
| + | 0006: | ||
| + | 0007: | ||
| + | 0008: | ||
| + | 0009: | ||
| + | 000A: | ||
| + | 000B: | ||
| + | 000C: | ||
| + | 000D: | ||
| + | 000E: | ||
| + | 000F: | ||
| + | 0010: | ||
| + | 0011: | ||
| + | 0012: | ||
| + | 0013: | ||
| + | 0014: | ||
| + | 0015: | ||
| + | 0016: | ||
| + | 0017: | ||
| + | 0018: | ||
| + | 0019: | ||
| + | 001A: | ||
| + | 001B: | ||
| + | 001C: | ||
| + | 001D: | ||
| + | 001E: | ||
| + | 001F: | ||
| + | DRAMC_DQSCTL1[0e0]=13000000 | ||
| + | DRAMC_DQSGCTL[124]=80000033 | ||
| + | rank 0 coarse = 15 | ||
| + | rank 0 fine = 48 | ||
| + | B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 | ||
| + | opt_dle value:9 | ||
| + | DRAMC_DDR2CTL[07c]=C287221D | ||
| + | DRAMC_PADCTL4[0e4]=000022B3 | ||
| + | DRAMC_DQIDLY1[210]=0E0F0B0E | ||
| + | DRAMC_DQIDLY2[214]=0C0F0D0E | ||
| + | DRAMC_DQIDLY3[218]=0C0D090C | ||
| + | DRAMC_DQIDLY4[21c]=0D0B0E0A | ||
| + | DRAMC_R0DELDLY[018]=0000201F | ||
| + | ================================================================== | ||
| + | RX DQS perbit delay software calibration | ||
| + | ================================================================== | ||
| + | 1.0-15 bit dq delay value | ||
| + | ================================================================== | ||
| + | bit| | ||
| + | -------------------------------------- | ||
| + | 0 | 13 11 14 13 13 11 15 12 11 9 | ||
| + | 10 | 12 11 9 11 10 9 | ||
| + | -------------------------------------- | ||
| + | |||
| + | ================================================================== | ||
| + | 2.dqs window | ||
| + | x=pass dqs delay value (min~max)center | ||
| + | y=0-7bit DQ of every group | ||
| + | input delay:DQS0 =31 DQS1 = 32 | ||
| + | ================================================================== | ||
| + | bit | ||
| + | 0 (0~60)30 | ||
| + | 1 (1~61)31 | ||
| + | 2 (1~60)30 | ||
| + | 3 (1~60)30 | ||
| + | 4 (1~60)30 | ||
| + | 5 (0~58)29 | ||
| + | 6 (1~60)30 | ||
| + | 7 (1~61)31 | ||
| + | ================================================================== | ||
| + | 3.dq delay value last | ||
| + | ================================================================== | ||
| + | bit| 0 1 2 3 4 5 6 7 8 9 | ||
| + | -------------------------------------- | ||
| + | 0 | 14 11 15 14 14 13 15 12 12 9 | ||
| + | 10 | 13 12 10 14 11 13 | ||
| + | ================================================================== | ||
| + | ================================================================== | ||
| + | | ||
| + | ================================================================== | ||
| + | DQS loop = 15, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[0]=15, | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[1]=15, | ||
| + | DQ loop=15, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqdly_pass[0]=15, | ||
| + | dqs_perbyte_dly.last_dqdly_pass[1]=15, | ||
| + | byte:0, (DQS, | ||
| + | byte:1, (DQS, | ||
| + | DRAMC_DQODLY1[200]=88888888 | ||
| + | DRAMC_DQODLY2[204]=88888888 | ||
| + | 20, | ||
| + | [EMI] DRAMC calibration passed | ||
| + | |||
| + | =================================================================== | ||
| + | MT7621 | ||
| + | CPU=500000000 HZ BUS=166666666 HZ | ||
| + | =================================================================== | ||
| + | |||
| + | |||
| + | U-Boot 1.1.3 (Jun 25 2020 - 13:46:13) | ||
| + | |||
| + | Board: MediaTek APSoC DRAM: 128 MB | ||
| + | |||
| + | Config XHCI 40M PLL | ||
| + | MediaTek SPI flash driver, SPI clock: 31MHz | ||
| + | spi device id: 1c 70 18 1c | ||
| + | find flash: EN25QH128A | ||
| + | *** Warning - bad CRC, using default environment | ||
| + | |||
| + | ============================================ | ||
| + | MediaTek U-Boot Version: 5.0.1.0-6 | ||
| + | -------------------------------------------- | ||
| + | ASIC MT7621A DualCore (MAC to MT7530 Mode) | ||
| + | DRAM_CONF_FROM: | ||
| + | DRAM_TYPE: DDR3 | ||
| + | DRAM bus: 16 bit | ||
| + | Xtal Mode=3 OCP Ratio=1/3 | ||
| + | Flash component: SPI Flash | ||
| + | Date:Jun 25 2020 Time: | ||
| + | ============================================ | ||
| + | icache: sets:256, ways:4, linesz:32, total: | ||
| + | dcache: sets:256, ways:4, linesz:32, total: | ||
| + | |||
| + | #### The CPU freq = 880 MHZ #### | ||
| + | | ||
| + | |||
| + | Reset MT7530 | ||
| + | set LAN/WAN WLLLL | ||
| + | |||
| + | Please choose the operation: | ||
| + | 0: Load system code then write to Flash via Serial. | ||
| + | 1: Load system code to SDRAM via TFTP. | ||
| + | 2: Load system code then write to Flash via TFTP. | ||
| + | 3: Boot system code via Flash (default). | ||
| + | 4: Enter boot command line interface. | ||
| + | 7: Load U-Boot code then write to Flash via Serial. | ||
| + | 9: Load U-Boot code then write to Flash via TFTP. 0 | ||
| + | |||
| + | |||
| + | 3: System Boot system code via Flash. | ||
| + | ## Checking image at bc050000 ... | ||
| + | Image Name: | ||
| + | Image Type: MIPS Linux Kernel Image (lzma compressed) | ||
| + | Data Size: 1777547 Bytes = 1.7 MB | ||
| + | Load Address: 81001000 | ||
| + | Entry Point: | ||
| + | | ||
| + | | ||
| + | No initrd | ||
| + | ## Transferring control to Linux (at address 81001000) ... | ||
| + | ## Giving linux memsize in MB, 128 | ||
| + | |||
| + | Starting kernel ... | ||
| + | |||
| + | [ 0.000000] Linux version 4.4.198 (dev@runner-rztzusz-project-2117-concurrent-0) (gcc version 5.4.0 (LEDE GCC 5.4.0 2.6.0-dev-2410171622-2635b5d54) ) #0 SMP Fri Nov 8 04:20:44 UTC 2024 | ||
| + | [ 0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3 | ||
| + | [ 0.000000] bootconsole [early0] enabled | ||
| + | [ 0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.000000] MIPS: machine is SNR-CPE-ME2-Lite | ||
| + | [ 0.000000] Determined physical RAM map: | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] Initrd not found or empty - disabling initrd | ||
| + | [ 0.000000] Zone ranges: | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] Movable zone start for each node | ||
| + | [ 0.000000] Early memory node ranges | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff] | ||
| + | [ 0.000000] VPE topology {2,2} total 4 | ||
| + | [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.000000] PERCPU: Embedded 10 pages/cpu @816a3000 s8576 r8192 d24192 u40960 | ||
| + | [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 | ||
| + | [ 0.000000] Kernel command line: console=ttyS0, | ||
| + | [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes) | ||
| + | [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) | ||
| + | [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) | ||
| + | [ 0.000000] Writing ErrCtl register=00011242 | ||
| + | [ 0.000000] Readback ErrCtl register=00011242 | ||
| + | [ 0.000000] Memory: 123996K/ | ||
| + | [ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, | ||
| + | [ 0.000000] Hierarchical RCU implementation. | ||
| + | [ 0.000000] NR_IRQS: | ||
| + | [ 0.000000] clocksource: | ||
| + | [ 0.000000] clocksource: | ||
| + | [ 0.000009] sched_clock: | ||
| + | [ 0.015464] Calibrating delay loop... 586.13 BogoMIPS (lpj=2930688) | ||
| + | [ 0.080694] pid_max: default: 32768 minimum: 301 | ||
| + | [ 0.090000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) | ||
| + | [ 0.103016] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) | ||
| + | [ 0.121126] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.121136] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.121146] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.121293] CPU1 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.227945] Synchronize counters for CPU 1: done. | ||
| + | [ 0.247353] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.247360] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.247367] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.247438] CPU2 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.348134] Synchronize counters for CPU 2: done. | ||
| + | [ 0.358934] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.358941] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.358948] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.359025] CPU3 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.467695] Synchronize counters for CPU 3: done. | ||
| + | [ 0.477121] Brought up 4 CPUs | ||
| + | [ 0.487542] clocksource: | ||
| + | [ 0.507020] futex hash table entries: 1024 (order: 3, 32768 bytes) | ||
| + | [ 0.519452] pinctrl core: initialized pinctrl subsystem | ||
| + | [ 0.531185] NET: Registered protocol family 16 | ||
| + | [ 0.570198] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.581304] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.592380] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.603915] mt7621-pci 1e140000.pcie: | ||
| + | [ 0.616113] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.930380] PCIe port 2 link down | ||
| + | [ 1.936814] PCI coherence region base: 0x60000000, mask/ | ||
| + | [ 1.983512] PCI host bridge to bus 0000:00 | ||
| + | [ 1.991581] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] | ||
| + | [ 2.005184] pci_bus 0000:00: root bus resource [io 0x1e160000-0x1e16ffff] | ||
| + | [ 2.018833] pci_bus 0000:00: root bus resource [??? 0x00000000 flags 0x0] | ||
| + | [ 2.032311] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] | ||
| + | [ 2.048831] pci 0000: | ||
| + | [ 2.064633] pci 0000: | ||
| + | [ 2.081836] pci 0000: | ||
| + | [ 2.095225] pci 0000: | ||
| + | [ 2.109542] pci 0000: | ||
| + | [ 2.123024] pci 0000: | ||
| + | [ 2.136507] pci 0000: | ||
| + | [ 2.149978] pci 0000: | ||
| + | [ 2.159806] pci 0000: | ||
| + | [ 2.173323] pci 0000: | ||
| + | [ 2.188703] pci 0000: | ||
| + | [ 2.204081] pci 0000: | ||
| + | [ 2.219457] pci 0000: | ||
| + | [ 2.229272] pci 0000: | ||
| + | [ 2.245169] clocksource: | ||
| + | [ 2.256863] NET: Registered protocol family 2 | ||
| + | [ 2.266229] TCP established hash table entries: 1024 (order: 0, 4096 bytes) | ||
| + | [ 2.279979] TCP bind hash table entries: 1024 (order: 1, 8192 bytes) | ||
| + | [ 2.292573] TCP: Hash tables configured (established 1024 bind 1024) | ||
| + | [ 2.305252] UDP hash table entries: 256 (order: 1, 8192 bytes) | ||
| + | [ 2.316770] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) | ||
| + | [ 2.329465] NET: Registered protocol family 1 | ||
| + | [ 2.349934] squashfs: version 4.0 (2009/ | ||
| + | [ 2.361476] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc. | ||
| + | [ 2.383622] io scheduler noop registered | ||
| + | [ 2.391444] io scheduler deadline registered (default) | ||
| + | [ 2.402941] Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled | ||
| + | [ 2.416745] console [ttyS0] disabled | ||
| + | [ 2.441744] console [ttyS0] enabled0 at MMIO 0x1e000c00 (irq = 33, base_baud = 3125000) is a 16550A | ||
| + | [ 2.441744] console [ttyS0] enabled | ||
| + | [ 2.455599] bootconsole [early0] disabled | ||
| + | [ 2.455599] bootconsole [early0] disabled | ||
| + | [ 2.475192] m25p80 spi32766.0: en25qh128 (16384 Kbytes) | ||
| + | [ 2.485742] 4 ofpart partitions found on MTD device spi32766.0 | ||
| + | [ 2.497408] Creating 4 MTD partitions on " | ||
| + | [ 2.507691] 0x000000000000-0x000000030000 : " | ||
| + | [ 2.519694] 0x000000030000-0x000000040000 : " | ||
| + | [ 2.530970] 0x000000040000-0x000000050000 : " | ||
| + | [ 2.542397] 0x000000050000-0x000001000000 : " | ||
| + | [ 2.565627] no rootfs found after FIT image in " | ||
| + | [ 2.597435] 2 uimage-fw partitions found on MTD device firmware | ||
| + | [ 2.609293] 0x000000050000-0x000000210000 : " | ||
| + | [ 2.620487] 0x000000210000-0x000001000000 : " | ||
| + | [ 2.631568] mtd: device 5 (rootfs) set to be root filesystem | ||
| + | [ 2.642991] 1 squashfs-split partitions found on MTD device rootfs | ||
| + | [ 2.655377] 0x0000008a0000-0x000001000000 : " | ||
| + | [ 2.667810] libphy: Fixed MDIO Bus: probed | ||
| + | [ 2.715416] libphy: mdio: probed | ||
| + | [ 2.722438] mtk_soc_eth 1e100000.ethernet: | ||
| + | [ 2.739275] mtk_soc_eth 1e100000.ethernet: | ||
| + | [ 2.760832] mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 10 | ||
| + | [ 2.777622] mtk_soc_eth 1e100000.ethernet: | ||
| + | [ 2.794485] mtk_soc_eth 1e100000.ethernet: | ||
| + | [ 2.815947] mtk_soc_eth 1e100000.ethernet eth1: mediatek frame engine at 0xbe100000, irq 10 | ||
| + | [ 2.833688] mt7621_wdt 1e000100.wdt: | ||
| + | [ 2.844514] NET: Registered protocol family 10 | ||
| + | [ 2.854822] NET: Registered protocol family 17 | ||
| + | [ 2.863829] bridge: automatic filtering via arp/ | ||
| + | [ 2.889128] Bridge firewalling registered | ||
| + | [ 2.897162] 8021q: 802.1Q VLAN Support v1.8 | ||
| + | [ 2.945292] mt753x gsw: Switch is MediaTek MT7530 rev 1 | ||
| + | [ 2.982021] libphy: mt753x_mdio: | ||
| + | [ 2.995612] hctosys: unable to open rtc device (rtc0) | ||
| + | [ 3.011484] VFS: Mounted root (squashfs filesystem) readonly on device 31:5. | ||
| + | [ 3.026184] Freeing unused kernel memory: 196K | ||
| + | [ 3.035062] This architecture does not have kernel memory protection. | ||
| + | [ 3.685411] init: Console is alive | ||
| + | [ 3.692417] init: - watchdog - | ||
| + | [ 4.927173] kmodloader: loading kernel modules from / | ||
| + | [ 4.979704] kmodloader: done loading kernel modules from / | ||
| + | [ 4.995448] init: - preinit - | ||
| + | [ 5.600109] mt753x gsw: Port 1 Link is Up - 1Gbps/ | ||
| + | [ 5.849417] random: jshn: uninitialized urandom read (4 bytes read, 108 bits of entropy available) | ||
| + | [ 5.964007] random: jshn: uninitialized urandom read (4 bytes read, 108 bits of entropy available) | ||
| + | [ 6.125210] random: jshn: uninitialized urandom read (4 bytes read, 109 bits of entropy available) | ||
| + | [ 6.224065] random: jshn: uninitialized urandom read (4 bytes read, 110 bits of entropy available) | ||
| + | [ 6.307869] random: jshn: uninitialized urandom read (4 bytes read, 111 bits of entropy available) | ||
| + | / | ||
| + | Press the [f] key and hit [enter] to enter failsafe mode | ||
| + | Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level | ||
| + | [ 9.615235] random: nonblocking pool is initialized | ||
| + | [ 9.659598] jffs2: notice: (451) jffs2_build_xattr_subsystem: | ||
| + | [ 9.692291] mount_root: switching to jffs2 overlay | ||
| + | [ 9.716663] urandom-seed: | ||
| + | [ 9.966277] procd: - early - | ||
| + | [ 9.972120] procd: - watchdog - | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | Please press Enter to activate this console. | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | 1 | ||
| + | card 1 -cra0 | ||
| + | 1 | ||
| + | card 2 -cra0 -crai0 | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
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| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | 1 | ||
| + | card 1 -cra0 | ||
| + | 1 | ||
| + | card 2 -cra0 -crai0 | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | </ | ||
| </ | </ | ||
| ==== OpenWrt bootlog ==== | ==== OpenWrt bootlog ==== | ||
| <WRAP bootlog> | <WRAP bootlog> | ||
| - | < | + | < |
| - | </ | + | |
| - | ===== Notes ===== | + | =================================================================== |
| - | //Space for additional notes, links to forum threads or other resources.// | + | |
| + | CPU=500000000 HZ BUS=166666666 HZ | ||
| + | ================================================================== | ||
| + | Change MPLL source from XTAL to CR... | ||
| + | do MEMPLL setting.. | ||
| + | MEMPLL Config : 0x11100000 | ||
| + | 3PLL mode + External loopback | ||
| + | === XTAL-40Mhz === DDR-1200Mhz === | ||
| + | PLL2 FB_DL: 0xf, 1/0 = 570/454 3D000000 | ||
| + | PLL3 FB_DL: 0xf, 1/0 = 589/435 3D000000 | ||
| + | PLL4 FB_DL: 0x17, 1/0 = 540/484 5D000000 | ||
| + | do DDR setting..[01F40000] | ||
| + | Apply DDR3 Setting...(use customer AC) | ||
| + | 0 8 | ||
| + | -------------------------------------------------------------------------------- | ||
| + | 0000: | ||
| + | 0001: | ||
| + | 0002: | ||
| + | 0003: | ||
| + | 0004: | ||
| + | 0005: | ||
| + | 0006: | ||
| + | 0007: | ||
| + | 0008: | ||
| + | 0009: | ||
| + | 000A: | ||
| + | 000B: | ||
| + | 000C: | ||
| + | 000D: | ||
| + | 000E: | ||
| + | 000F: | ||
| + | 0010: | ||
| + | 0011: | ||
| + | 0012: | ||
| + | 0013: | ||
| + | 0014: | ||
| + | 0015: | ||
| + | 0016: | ||
| + | 0017: | ||
| + | 0018: | ||
| + | 0019: | ||
| + | 001A: | ||
| + | 001B: | ||
| + | 001C: | ||
| + | 001D: | ||
| + | 001E: | ||
| + | 001F: | ||
| + | DRAMC_DQSCTL1[0e0]=13000000 | ||
| + | DRAMC_DQSGCTL[124]=80000033 | ||
| + | rank 0 coarse = 15 | ||
| + | rank 0 fine = 48 | ||
| + | B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 | ||
| + | opt_dle value:9 | ||
| + | DRAMC_DDR2CTL[07c]=C287221D | ||
| + | DRAMC_PADCTL4[0e4]=000022B3 | ||
| + | DRAMC_DQIDLY1[210]=0E0F0B0F | ||
| + | DRAMC_DQIDLY2[214]=0D0F0D0F | ||
| + | DRAMC_DQIDLY3[218]=0C0E090C | ||
| + | DRAMC_DQIDLY4[21c]=0D0C0E0B | ||
| + | DRAMC_R0DELDLY[018]=0000201F | ||
| + | ================================================================== | ||
| + | RX DQS perbit delay software calibration | ||
| + | ================================================================== | ||
| + | 1.0-15 bit dq delay value | ||
| + | ================================================================== | ||
| + | bit| | ||
| + | -------------------------------------- | ||
| + | 0 | 13 11 14 13 13 11 15 12 11 9 | ||
| + | 10 | 12 11 9 11 10 9 | ||
| + | -------------------------------------- | ||
| - | | + | ================================================================== |
| + | 2.dqs window | ||
| + | x=pass dqs delay value (min~max)center | ||
| + | y=0-7bit DQ of every group | ||
| + | input delay:DQS0 =31 DQS1 = 32 | ||
| + | ================================================================== | ||
| + | bit | ||
| + | 0 (1~58)29 | ||
| + | 1 (1~61)31 | ||
| + | 2 (1~58)29 | ||
| + | 3 (1~60)30 | ||
| + | 4 (1~58)29 | ||
| + | 5 (1~58)29 | ||
| + | 6 (1~58)29 | ||
| + | 7 (0~61)30 | ||
| + | ================================================================== | ||
| + | 3.dq delay value last | ||
| + | ================================================================== | ||
| + | bit| 0 1 2 3 4 5 6 7 8 | ||
| + | -------------------------------------- | ||
| + | 0 | 15 11 15 14 15 13 15 13 12 9 | ||
| + | 10 | 14 12 11 14 12 13 | ||
| + | ================================================================== | ||
| + | ================================================================== | ||
| + | | ||
| + | ================================================================== | ||
| + | DQS loop = 15, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[0]=15, | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[1]=15, | ||
| + | DQ loop=15, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqdly_pass[0]=15, | ||
| + | dqs_perbyte_dly.last_dqdly_pass[1]=15, | ||
| + | byte:0, (DQS, | ||
| + | byte:1, (DQS, | ||
| + | DRAMC_DQODLY1[200]=88888888 | ||
| + | DRAMC_DQODLY2[204]=88888888 | ||
| + | 20, | ||
| + | [EMI] DRAMC calibration passed | ||
| + | =================================================================== | ||
| + | MT7621 | ||
| + | CPU=500000000 HZ BUS=166666666 HZ | ||
| + | =================================================================== | ||
| + | |||
| + | |||
| + | U-Boot 1.1.3 (Jun 25 2020 - 13:46:13) | ||
| + | |||
| + | Board: MediaTek APSoC DRAM: 128 MB | ||
| + | |||
| + | Config XHCI 40M PLL | ||
| + | MediaTek SPI flash driver, SPI clock: 31MHz | ||
| + | spi device id: 1c 70 18 1c | ||
| + | find flash: EN25QH128A | ||
| + | *** Warning - bad CRC, using default environment | ||
| + | |||
| + | ============================================ | ||
| + | MediaTek U-Boot Version: 5.0.1.0-6 | ||
| + | -------------------------------------------- | ||
| + | ASIC MT7621A DualCore (MAC to MT7530 Mode) | ||
| + | DRAM_CONF_FROM: | ||
| + | DRAM_TYPE: DDR3 | ||
| + | DRAM bus: 16 bit | ||
| + | Xtal Mode=3 OCP Ratio=1/3 | ||
| + | Flash component: SPI Flash | ||
| + | Date:Jun 25 2020 Time: | ||
| + | ============================================ | ||
| + | icache: sets:256, ways:4, linesz:32, total:32768 | ||
| + | dcache: sets:256, ways:4, linesz:32, total:32768 | ||
| + | |||
| + | #### The CPU freq = 880 MHZ #### | ||
| + | | ||
| + | |||
| + | Reset MT7530 | ||
| + | set LAN/WAN WLLLL | ||
| + | |||
| + | Please choose the operation: | ||
| + | 0: Load system code then write to Flash via Serial. | ||
| + | 1: Load system code to SDRAM via TFTP. | ||
| + | 2: Load system code then write to Flash via TFTP. | ||
| + | 3: Boot system code via Flash (default). | ||
| + | 4: Enter boot command line interface. | ||
| + | 7: Load U-Boot code then write to Flash via Serial. | ||
| + | 9: Load U-Boot code then write to Flash via TFTP. 0 | ||
| + | |||
| + | |||
| + | 3: System Boot system code via Flash. | ||
| + | ## Checking image at bc050000 ... | ||
| + | Image Name: | ||
| + | Image Type: MIPS Linux Kernel Image (uncompressed) | ||
| + | Data Size: 2811990 Bytes = 2.7 MB | ||
| + | Load Address: 80001000 | ||
| + | Entry Point: | ||
| + | | ||
| + | OK | ||
| + | No initrd | ||
| + | ## Transferring control to Linux (at address 80001000) ... | ||
| + | ## Giving linux memsize in MB, 128 | ||
| + | |||
| + | Starting kernel ... | ||
| + | |||
| + | |||
| + | |||
| + | OpenWrt kernel loader for MIPS based SoC | ||
| + | Copyright (C) 2011 Gabor Juhos < | ||
| + | Decompressing kernel... done! | ||
| + | Starting kernel at 80001000... | ||
| + | |||
| + | [ 0.000000] Linux version 5.15.167 (builder@buildhost) (mipsel-openwrt-linux-musl-gcc (OpenWrt GCC 12.3.0 r24106-10cc5fcd00) 12.3.0, GNU ld (GNU Binutils) 2.40.0) #0 SMP Mon Sep 23 12:34:46 2024 | ||
| + | [ 0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3 | ||
| + | [ 0.000000] printk: bootconsole [early0] enabled | ||
| + | [ 0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.000000] MIPS: machine is SNR-CPE-ME2-Lite | ||
| + | [ 0.000000] Initrd not found or empty - disabling initrd | ||
| + | [ 0.000000] VPE topology {2,2} total 4 | ||
| + | [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.000000] Zone ranges: | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] Movable zone start for each node | ||
| + | [ 0.000000] Early memory node ranges | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff] | ||
| + | [ 0.000000] percpu: Embedded 12 pages/cpu s17808 r8192 d23152 u49152 | ||
| + | [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 32480 | ||
| + | [ 0.000000] Kernel command line: console=ttyS0, | ||
| + | [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear) | ||
| + | [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear) | ||
| + | [ 0.000000] Writing ErrCtl register=00011a42 | ||
| + | [ 0.000000] Readback ErrCtl register=00011a42 | ||
| + | [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off | ||
| + | [ 0.000000] Memory: 119220K/ | ||
| + | [ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, | ||
| + | [ 0.000000] rcu: Hierarchical RCU implementation. | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. | ||
| + | [ 0.000000] NR_IRQS: 256 | ||
| + | [ 0.000000] clocksource: | ||
| + | [ 0.000004] sched_clock: | ||
| + | [ 0.016015] Calibrating delay loop... 586.13 BogoMIPS (lpj=2930688) | ||
| + | [ 0.088318] pid_max: default: 32768 minimum: 301 | ||
| + | [ 0.098270] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) | ||
| + | [ 0.112686] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) | ||
| + | [ 0.131872] rcu: Hierarchical SRCU implementation. | ||
| + | [ 0.142081] smp: Bringing up secondary CPUs ... | ||
| + | [ 0.151852] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.151876] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.151891] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.151935] CPU1 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.211621] Synchronize counters for CPU 1: done. | ||
| + | [ 0.273814] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.273834] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.273845] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.273872] CPU2 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.332791] Synchronize counters for CPU 2: done. | ||
| + | [ 0.393166] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.393186] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.393197] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.393228] CPU3 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.452365] Synchronize counters for CPU 3: done. | ||
| + | [ 0.511961] smp: Brought up 1 node, 4 CPUs | ||
| + | [ 0.525040] clocksource: | ||
| + | [ 0.544530] futex hash table entries: 1024 (order: 3, 32768 bytes, linear) | ||
| + | [ 0.558435] pinctrl core: initialized pinctrl subsystem | ||
| + | [ 0.570306] NET: Registered PF_NETLINK/ | ||
| + | [ 0.582772] thermal_sys: | ||
| + | [ 0.613982] clocksource: | ||
| + | [ 0.625264] NET: Registered PF_INET protocol family | ||
| + | [ 0.635042] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear) | ||
| + | [ 0.650258] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear) | ||
| + | [ 0.666808] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) | ||
| + | [ 0.682164] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear) | ||
| + | [ 0.697372] TCP bind hash table entries: 1024 (order: 1, 8192 bytes, linear) | ||
| + | [ 0.711376] TCP: Hash tables configured (established 1024 bind 1024) | ||
| + | [ 0.724133] UDP hash table entries: 256 (order: 1, 8192 bytes, linear) | ||
| + | [ 0.737048] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear) | ||
| + | [ 0.751229] NET: Registered PF_UNIX/ | ||
| + | [ 0.762430] PCI: CLS 0 bytes, default 32 | ||
| + | [ 0.772885] workingset: timestamp_bits=14 max_order=15 bucket_order=1 | ||
| + | [ 0.790995] squashfs: version 4.0 (2009/ | ||
| + | [ 0.802572] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc. | ||
| + | [ 0.823472] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251) | ||
| + | [ 0.841929] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.853472] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.864897] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.876439] mt7621-pci 1e140000.pcie: | ||
| + | [ 0.889712] mt7621-pci 1e140000.pcie: | ||
| + | [ 0.907191] mt7621-pci 1e140000.pcie: | ||
| + | [ 0.923403] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.293983] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.307755] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.317407] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.327105] PCI coherence region base: 0x60000000, mask/ | ||
| + | [ 1.341292] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.353818] pci_bus 0000:00: root bus resource [bus 00-ff] | ||
| + | [ 1.364696] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] | ||
| + | [ 1.378340] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] | ||
| + | [ 1.390656] pci 0000: | ||
| + | [ 1.402546] pci 0000: | ||
| + | [ 1.414984] pci 0000: | ||
| + | [ 1.427527] pci 0000: | ||
| + | [ 1.435375] pci 0000: | ||
| + | [ 1.447553] pci 0000: | ||
| + | [ 1.459484] pci 0000: | ||
| + | [ 1.471879] pci 0000: | ||
| + | [ 1.484404] pci 0000: | ||
| + | [ 1.492230] pci 0000: | ||
| + | [ 1.505558] pci 0000: | ||
| + | [ 1.521417] pci 0000: | ||
| + | [ 1.537544] pci 0000: | ||
| + | [ 1.549430] pci 0000: | ||
| + | [ 1.561949] pci 0000: | ||
| + | [ 1.575310] pci 0000: | ||
| + | [ 1.585625] pci 0000: | ||
| + | [ 1.597691] pci 0000: | ||
| + | [ 1.611189] pci 0000: | ||
| + | [ 1.625542] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 | ||
| + | [ 1.638938] pci 0000: | ||
| + | [ 1.650814] pci 0000: | ||
| + | [ 1.665136] pci 0000: | ||
| + | [ 1.679467] pci 0000: | ||
| + | [ 1.693907] pci 0000: | ||
| + | [ 1.702271] pci 0000: | ||
| + | [ 1.715433] pci 0000: | ||
| + | [ 1.746269] pci 0000: | ||
| + | [ 1.756580] pci 0000: | ||
| + | [ 1.768649] pci 0000: | ||
| + | [ 1.782134] pci 0000: | ||
| + | [ 1.796484] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02 | ||
| + | [ 1.809665] pci 0000: | ||
| + | [ 1.822735] pci 0000: | ||
| + | [ 1.836563] pci 0000: | ||
| + | [ 1.849696] pci 0000: | ||
| + | [ 1.863517] pci 0000: | ||
| + | [ 1.877008] pci 0000: | ||
| + | [ 1.891344] pci 0000: | ||
| + | [ 1.904816] pci 0000: | ||
| + | [ 1.919172] pci 0000: | ||
| + | [ 1.932641] pci 0000: | ||
| + | [ 1.946129] pci 0000: | ||
| + | [ 1.958218] pci 0000: | ||
| + | [ 1.970316] pci 0000: | ||
| + | [ 1.983796] pci 0000: | ||
| + | [ 1.993634] pci 0000: | ||
| + | [ 2.005743] pci 0000: | ||
| + | [ 2.019215] pci 0000: | ||
| + | [ 2.033557] pci 0000: | ||
| + | [ 2.048954] pci 0000: | ||
| + | [ 2.064334] pci 0000: | ||
| + | [ 2.079706] pci 0000: | ||
| + | [ 2.089537] pci 0000: | ||
| + | [ 2.101641] pci 0000: | ||
| + | [ 2.115112] pci 0000: | ||
| + | [ 2.132068] Serial: 8250/16550 driver, 16 ports, IRQ sharing enabled | ||
| + | [ 2.149284] printk: console [ttyS0] disabled | ||
| + | [ 2.157822] 1e000c00.uartlite: | ||
| + | [ 2.175765] printk: console [ttyS0] enabled | ||
| + | [ 2.175765] printk: console [ttyS0] enabled | ||
| + | [ 2.192308] printk: bootconsole [early0] disabled | ||
| + | [ 2.192308] printk: bootconsole [early0] disabled | ||
| + | [ 2.214990] spi-mt7621 1e000b00.spi: | ||
| + | [ 2.226934] spi-nor spi0.0: en25qh128 (16384 Kbytes) | ||
| + | [ 2.236998] 4 fixed-partitions partitions found on MTD device spi0.0 | ||
| + | [ 2.249705] OF: Bad cell count for / | ||
| + | [ 2.264315] OF: Bad cell count for / | ||
| + | [ 2.279412] OF: Bad cell count for / | ||
| + | [ 2.294094] OF: Bad cell count for / | ||
| + | [ 2.308958] Creating 4 MTD partitions on " | ||
| + | [ 2.318538] 0x000000000000-0x000000030000 : " | ||
| + | [ 2.329585] 0x000000030000-0x000000040000 : " | ||
| + | [ 2.340534] 0x000000040000-0x000000050000 : " | ||
| + | [ 2.351638] 0x000000050000-0x000001000000 : " | ||
| + | [ 2.363205] 2 uimage-fw partitions found on MTD device firmware | ||
| + | [ 2.375075] Creating 2 MTD partitions on " | ||
| + | [ 2.384998] 0x000000000000-0x0000002ae896 : " | ||
| + | [ 2.394895] mtd: partition " | ||
| + | [ 2.412464] 0x0000002ae896-0x000000fb0000 : " | ||
| + | [ 2.422415] mtd: partition " | ||
| + | [ 2.441576] mtd: setting mtd5 (rootfs) as root device | ||
| + | [ 2.451808] 1 squashfs-split partitions found on MTD device rootfs | ||
| + | [ 2.464136] 0x0000006a0000-0x000000fb0000 : " | ||
| + | [ 2.617021] mt7530-mdio mdio-bus: | ||
| + | [ 2.639264] mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 23 | ||
| + | [ 2.659735] mtk_soc_eth 1e100000.ethernet wan: mediatek frame engine at 0xbe100000, irq 23 | ||
| + | [ 2.679110] i2c_dev: i2c /dev entries driver | ||
| + | [ 2.690678] NET: Registered PF_INET6 protocol family | ||
| + | [ 2.703060] Segment Routing with IPv6 | ||
| + | [ 2.710482] In-situ OAM (IOAM) with IPv6 | ||
| + | [ 2.718456] NET: Registered PF_PACKET protocol family | ||
| + | [ 2.728656] bridge: filtering via arp/ | ||
| + | [ 2.754947] 8021q: 802.1Q VLAN Support v1.8 | ||
| + | [ 2.769332] mt7530-mdio mdio-bus: | ||
| + | [ 2.805989] mt7530-mdio mdio-bus: | ||
| + | [ 2.820656] mt7530-mdio mdio-bus: | ||
| + | [ 2.825037] mt7530-mdio mdio-bus:1f lan1 (uninitialized): | ||
| + | [ 2.858889] mt7530-mdio mdio-bus:1f lan2 (uninitialized): | ||
| + | [ 2.881913] mt7530-mdio mdio-bus:1f lan3 (uninitialized): | ||
| + | [ 2.905071] mt7530-mdio mdio-bus:1f lan4 (uninitialized): | ||
| + | [ 2.927508] DSA: tree 0 setup | ||
| + | [ 2.934927] clk: Disabling unused clocks | ||
| + | [ 2.948253] VFS: Mounted root (squashfs filesystem) readonly on device 31:5. | ||
| + | [ 2.966516] Freeing unused kernel image (initmem) memory: 1264K | ||
| + | [ 2.978390] This architecture does not have kernel memory protection. | ||
| + | [ 2.991246] Run /sbin/init as init process | ||
| + | [ 3.421492] init: Console is alive | ||
| + | [ 3.428859] init: - watchdog - | ||
| + | [ 4.118159] kmodloader: loading kernel modules from / | ||
| + | [ 4.179112] kmodloader: done loading kernel modules from / | ||
| + | [ 4.204320] init: - preinit - | ||
| + | [ 5.005593] random: jshn: uninitialized urandom read (4 bytes read) | ||
| + | [ 5.129842] random: jshn: uninitialized urandom read (4 bytes read) | ||
| + | [ 5.175246] random: jshn: uninitialized urandom read (4 bytes read) | ||
| + | [ 5.465284] mtk_soc_eth 1e100000.ethernet eth0: configuring for fixed/rgmii link mode | ||
| + | [ 5.485851] mtk_soc_eth 1e100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx | ||
| + | [ 5.486267] mt7530-mdio mdio-bus:1f lan1: configuring for phy/gmii link mode | ||
| + | [ 5.517278] IPv6: ADDRCONF(NETDEV_CHANGE): | ||
| + | Press the [f] key and hit [enter] to enter failsafe mode | ||
| + | Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level | ||
| + | [ 7.726247] jffs2: notice: (435) jffs2_build_xattr_subsystem: | ||
| + | [ 7.759623] mount_root: switching to jffs2 overlay | ||
| + | [ 7.779007] overlayfs: upper fs does not support tmpfile. | ||
| + | [ 7.800876] urandom-seed: | ||
| + | [ 7.912457] procd: - early - | ||
| + | [ 7.918542] procd: - watchdog - | ||
| + | [ 8.523182] procd: - watchdog - | ||
| + | [ 8.530455] procd: - ubus - | ||
| + | [ 8.596536] random: ubusd: uninitialized urandom read (4 bytes read) | ||
| + | [ 8.612089] random: ubusd: uninitialized urandom read (4 bytes read) | ||
| + | [ 8.710726] random: ubusd: uninitialized urandom read (4 bytes read) | ||
| + | [ 8.733230] procd: - init - | ||
| + | Please press Enter to activate this console. | ||
| + | [ 9.291993] kmodloader: loading kernel modules from / | ||
| + | [ 9.527067] Loading modules backported from Linux version v6.1.110-0-g5f55cad62cc9d | ||
| + | [ 9.542363] Backport generated by backports.git v6.1.110-1-0-g965f73fc | ||
| + | [ 9.750124] pci 0000: | ||
| + | [ 9.761534] mt7603e 0000: | ||
| + | [ 9.773725] mt7603e 0000: | ||
| + | [ 9.792166] mt7603e 0000: | ||
| + | [ 9.803377] mt7603e 0000: | ||
| + | [ 9.854015] mt7603e 0000: | ||
| + | [ | ||
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| + | </ | ||
| + | </ | ||
| + | |||
| + | ===== Notes ===== | ||
| + | * [[commit>? | ||
| + | * [[https:// | ||
| ===== Tags ===== | ===== Tags ===== | ||
| - | <WRAP BOX> | ||
| - | FIXME //Add tags below, then remove this fixme.// | ||
| - | </ | ||
| - | [[meta: | + | {{tag>U-boot 2core MT7621 128RAM 16Flash GigabitEthernet wlan 802.11ac 4Ant 5Port SPI Serial 1button "12v powered" |
| - | {{tag>EXAMPLETAG}} | + | |