Ruijie RG-EW1200G PRO v1.1
Warning.!! Right now there is only a port for a rev1.1 of that router and the image was not tested on other revisions!
Hardware Highlights
Installation
Get rootshell using insructions from https://gist.github.com/ZIKH26/18693c67ee7d2f8d2c60231b19194c37
It'll be much easier to hack router using that extension: https://addons.mozilla.org/ru/firefox/addon/firefox-hackbar/
(This is the same thing that's being used on the picture)
Download and flash image
On computer:
python -m http.server
On router:
cd /tmp
wget http://:8000/factory.bin
mtd -r write factory.bin firmware
Flash Layout
0x000000000000-0x000000050000 : “u-boot” 0x000000050000-0x000000060000 : “u-boot-env” 0x000000060000-0x000000070000 : “Factory” 0x000000070000-0x000000080000 : “product_info” 0x000000080000-0x000000090000 : “kdump” 0x000000090000-0x000001000000 : “firmware” 0x00000033522c-0x000001000000 : “rootfs”
Upgrading OpenWrt
LuCI Web Upgrade Process
- Browse to
http://192.168.1.1/cgi-bin/luci/mini/system/upgrade/
LuCI Upgrade URL - Upload image file for sysupgrade to LuCI
- Wait for reboot
Terminal Upgrade Process
If you don't have a GUI (LuCI) available, you can alternatively upgrade via the command line. There are two command line methods for upgrading:
sysupgrade
mtd
Note: It is important that you put the firmware image into the ramdisk (/tmp) before you start flashing.
sysupgrade
- Login as root via SSH on 192.168.1.1, then enter the following commands:
cd /tmp wget http://downloads.openwrt.org/snapshots/trunk/XXX/xxx.abc sysupgrade /tmp/xxx.abc
mtd
If sysupgrade
does not support this router, use mtd
.
- Login as root via SSH on 192.168.1.1, then enter the following commands:
cd /tmp wget http://downloads.openwrt.org/snapshots/trunk/XXX/xxx.abc mtd write /tmp/xxx.abc linux && reboot
</WRAP>
Debricking
Failsafe mode
Basic configuration
→ Basic configuration After flashing, proceed with this.
Set up your Internet connection, configure wireless, configure USB port, etc.
Opening the case
Note: This will void your warranty!
There are some plastic pins holding the upper cover. Use something thin and break them
===== Bootlogs =====
==== OEM bootlog ====
=================================================================== MT7621 stage1 code Aug 28 2018 16:58:15 (ASIC) CPU=500000000 HZ BUS=166666666 HZ ================================================================== Change MPLL source from XTAL to CR... do MEMPLL setting.. MEMPLL Config : 0x11100000 3PLL mode + External loopback === XTAL-40Mhz === DDR-1200Mhz === PLL3 FB_DL: 0xc, 1/0 = 635/389 31000000 PLL4 FB_DL: 0xe, 1/0 = 685/339 39000000 PLL2 FB_DL: 0x12, 1/0 = 664/360 49000000 do DDR setting..[01F40000] Apply DDR3 Setting...(use customer AC) 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 -------------------------------------------------------------------------------- 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 000E:| 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 000F:| 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0010:| 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0011:| 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRAMC_DQSCTL1[0e0]=13000000 DRAMC_DQSGCTL[124]=80000033 rank 0 coarse = 15 rank 0 fine = 64 B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 opt_dle value:9 DRAMC_DDR2CTL[07c]=C287221D DRAMC_PADCTL4[0e4]=000022B3 DRAMC_DQIDLY1[210]=0C0C0A0E DRAMC_DQIDLY2[214]=0B0E0B0D DRAMC_DQIDLY3[218]=0A0D080B DRAMC_DQIDLY4[21c]=090A0B0A DRAMC_R0DELDLY[018]=00002020 ================================================================== RX DQS perbit delay software calibration ================================================================== 1.0-15 bit dq delay value ================================================================== bit| 0 1 2 3 4 5 6 7 8 9 -------------------------------------- 0 | 13 9 11 11 13 10 14 10 11 7 10 | 12 10 9 11 9 8 -------------------------------------- ================================================================== 2.dqs window x=pass dqs delay value (min~max)center y=0-7bit DQ of every group input delay:DQS0 =32 DQS1 = 32 ================================================================== bit DQS0 bit DQS1 0 (1~62)31 8 (1~63)32 1 (1~62)31 9 (1~62)31 2 (1~62)31 10 (1~62)31 3 (1~62)31 11 (1~64)32 4 (1~64)32 12 (1~62)31 5 (1~62)31 13 (1~63)32 6 (0~64)32 14 (1~62)31 7 (1~62)31 15 (0~62)31 ================================================================== 3.dq delay value last ================================================================== bit| 0 1 2 3 4 5 6 7 8 9 -------------------------------------- 0 | 14 10 12 12 13 11 14 11 11 8 10 | 13 10 10 11 10 9 ================================================================== ================================================================== TX perbyte calibration ================================================================== DQS loop = 15, cmp_err_1 = ffff0000 dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1 dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2 DQ loop=15, cmp_err_1 = ffff0000 dqs_perbyte_dly.last_dqdly_pass[0]=15, finish count=1 dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=2 byte:0, (DQS,DQ)=(8,8) byte:1, (DQS,DQ)=(8,8) DRAMC_DQODLY1[200]=88888888 DRAMC_DQODLY2[204]=88888888 20,data:88 [EMI] DRAMC calibration passed =================================================================== MT7621 stage1 code done CPU=500000000 HZ BUS=166666666 HZ =================================================================== U-Boot 1.1.3 (Nov 5 2019 - 18:15:22) Board: Ralink APSoC DRAM: 128 MB Config XHCI 40M PLL flash manufacture id: c2, device id 20 18 find flash: MX25L12805D product info crc check success 35635612 Erasing SPI Flash... . Writing to SPI Flash... . done ============================================ Ralink UBoot Version: 5.0.0.0 -------------------------------------------- ASIC MT7621A DualCore (MAC to MT7530 Mode) DRAM_CONF_FROM: Auto-Detection DRAM_TYPE: DDR3 DRAM bus: 16 bit Xtal Mode=3 OCP Ratio=1/3 Flash component: SPI Flash Date:Nov 5 2019 Time:18:15:22 ============================================ icache: sets:256, ways:4, linesz:32 ,total:32768 dcache: sets:256, ways:4, linesz:32 ,total:32768 #Reset_MT7530 Please choose the operation: 1: Load system code to SDRAM via TFTP. 2: Load system code then write to Flash via TFTP. 3: Boot system code via Flash (default). 4: Entr boot command line interface. 7: Load Boot Loader code then write to Flash via Serial. 9: Load Boot Loader code then write to Flash via TFTP. default: 3 0 Erasing SPI Flash... . Writing to SPI Flash... . done 3: System Boot system code via Flash. ## Booting image at bc090000 ... Image Name: MIPS OpenWrt Linux-3.10.108 Image Type: MIPS Linux Kernel Image (lzma compressed) Data Size: 2773484 Bytes = 2.6 MB Load Address: 81001000 Entry Point: 81001000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK Starting kernel ... LINUX started... THIS IS ASIC SDK 5.0.S.0 [ 0.000000] Linux version 3.10.108 (sdk@runner-h-ps1zdc-project-2-concurrent-1) (gcc version 4.8.3 (OpenWrt/Linaro GCC 4.8-2014.04 unknown) ) #1 SMP Wed Jun 21 14:08:46 UTC 2023 [ 0.000000] [ 0.000000] The CPU feqenuce set to 880 MHz [ 0.000000] GCMP present [ 0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc) [ 0.000000] Software DMA cache coherency [ 0.000000] MIPS: machine is EW1200G PROI [ 0.000000] Determined physical RAM map: [ 0.000000] memory: 08000000 @ 00000000 (usable) [ 0.000000] Initrd not found or empty - disabling initrd [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x00000000-0x00ffffff] [ 0.000000] Normal [mem 0x01000000-0x07ffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x00000000-0x07ffffff] [ 0.000000] Detected 3 available secondary CPU(s) [ 0.000000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes. [ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. [ 0.000000] PERCPU: Embedded 7 pages/cpu @81884000 s6080 r8192 d14400 u32768 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 [ 0.000000] Kernel command line: console=ttyS1,57600n8 root=/dev/mtdblock6 mtdparts=raspi:320k(u-boot)ro,64k(u-boot-env),64k(Factory),64k(product_info),64k(kdump),-(firmware) rootfstype=squashfs,jffs2 print-fatal-signals=1 [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes) [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [ 0.000000] Writing ErrCtl register=00008100 [ 0.000000] Readback ErrCtl register=00008100 [ 0.000000] Memory: 122128k/131072k available (5227k kernel code, 8944k reserved, 1910k data, 216k init, 0k highmem) [ 0.000000] Hierarchical RCU implementation. [ 0.000000] NR_IRQS:128 [ 0.000000] console [ttyS1] enabled [ 0.124000] Calibrating delay loop... 574.46 BogoMIPS (lpj=1148928) [ 0.156000] pid_max: default: 32768 minimum: 301 [ 0.160000] Mount-cache hash table entries: 512 [ 0.164000] launch: starting cpu1 [ 0.168000] launch: cpu1 gone! [ 0.168000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes. [ 0.168000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.168000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. [ 0.168000] CPU1 revision is: 0001992f (MIPS 1004Kc) [ 0.200000] Synchronize counters for CPU 1: done. [ 0.204000] launch: starting cpu2 [ 0.208000] launch: cpu2 gone! [ 0.208000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes. [ 0.208000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.208000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. [ 0.208000] CPU2 revision is: 0001992f (MIPS 1004Kc) [ 0.240000] Synchronize counters for CPU 2: done. [ 0.244000] launch: starting cpu3 [ 0.248000] launch: cpu3 gone! [ 0.248000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes. [ 0.248000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.248000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. [ 0.248000] CPU3 revision is: 0001992f (MIPS 1004Kc) [ 0.276000] Synchronize counters for CPU 3: done. [ 0.280000] Brought up 4 CPUs [ 0.284000] NET: Registered protocol family 16 [ 0.588000] release PCIe RST: RALINK_RSTCTRL = 7000000 [ 0.600000] PCIE PHY initialize [ 0.608000] ***** Xtal 40MHz ***** [ 0.612000] start MT7621 PCIe register access [ 1.212000] RALINK_RSTCTRL = 7000000 [ 1.220000] RALINK_CLKCFG1 = 77ffeff8 [ 1.224000] [ 1.224000] *************** MT7621 PCIe RC mode ************* [ 1.732000] PCIE1 no card, disable it(RST&CLK) [ 1.740000] PCIE2 no card, disable it(RST&CLK) [ 1.748000] pcie_link status = 0x1 [ 1.756000] RALINK_RSTCTRL= 1000000 [ 1.764000] *** Configure Device number setting of Virtual PCI-PCI bridge *** [ 1.776000] RALINK_PCI_PCICFG_ADDR = 21007f2 -> 21007f2 [ 1.788000] PCIE0 enabled [ 1.792000] interrupt enable status: 100000 [ 1.800000] Port 0 N_FTS = 1b105000 [ 1.808000] config reg done [ 1.812000] init_rt2880pci done [ 1.820000] gpio device register! [ 1.832000] bio: create slab <bio-0> at 0 [ 1.840000] ralink_gpio ralink_gpio.0: registering 32 gpios [ 1.852000] ralink_gpio ralink_gpio.0: registering 32 gpios [ 1.860000] ralink_gpio ralink_gpio.0: registering 32 gpios [ 1.876000] PCI host bridge to bus 0000:00 [ 1.884000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] [ 1.896000] pci_bus 0000:00: root bus resource [io 0x1e160000-0x1e16ffff] [ 1.912000] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] [ 1.928000] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 1.944000] pci 0000:00:00.0: BAR 0: can't assign mem (size 0x80000000) [ 1.956000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff] [ 1.968000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60100000-0x6010ffff] [ 1.984000] pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x600fffff 64bit] [ 1.996000] pci 0000:00:00.0: PCI bridge to [bus 01] [ 2.008000] pci 0000:00:00.0: bridge window [mem 0x60000000-0x600fffff] [ 2.020000] PCI: Enabling device 0000:00:00.0 (0004 -> 0006) [ 2.032000] BAR0 at slot 0 = 0 [ 2.040000] bus=0x0, slot = 0x0 [ 2.044000] res[0]->start = 0 [ 2.052000] res[0]->end = 0 [ 2.056000] res[1]->start = 60100000 [ 2.064000] res[1]->end = 6010ffff [ 2.068000] res[2]->start = 0 [ 2.076000] res[2]->end = 0 [ 2.080000] res[3]->start = 0 [ 2.088000] res[3]->end = 0 [ 2.092000] res[4]->start = 0 [ 2.100000] res[4]->end = 0 [ 2.104000] res[5]->start = 0 [ 2.112000] res[5]->end = 0 [ 2.116000] bus=0x1, slot = 0x0, irq=0x4 [ 2.124000] res[0]->start = 60000000 [ 2.132000] res[0]->end = 600fffff [ 2.136000] res[1]->start = 0 [ 2.144000] res[1]->end = 0 [ 2.148000] res[2]->start = 0 [ 2.156000] res[2]->end = 0 [ 2.160000] res[3]->start = 0 [ 2.168000] res[3]->end = 0 [ 2.172000] res[4]->start = 0 [ 2.176000] res[4]->end = 0 [ 2.184000] res[5]->start = 0 [ 2.188000] res[5]->end = 0 [ 2.196000] proc fast_bridge create start [ 2.204000] proc fast_bridge create successful [ 2.212000] Switching to clocksource Ralink Systick timer [ 2.224000] NET: Registered protocol family 2 [ 2.228000] Clockevents: could not switch to one-shot mode: [ 2.228000] Clockevents: could not switch to one-shot mode: [ 2.228000] MIPS is not functional. [ 2.228000] MIPS is not functional. [ 2.228000] Clockevents: could not switch to one-shot mode: MIPS is not functional. [ 2.228000] Could not switch to high resolution mode on CPU 0 [ 2.228000] Could not switch to high resolution mode on CPU 2 [ 2.228000] Could not switch to high resolution mode on CPU 3 [ 2.320000] Clockevents: could not switch to one-shot mode: MIPS is not functional. [ 2.336000] Could not switch to high resolution mode on CPU 1 [ 2.348000] TCP established hash table entries: 1024 (order: 1, 8192 bytes) [ 2.360000] TCP bind hash table entries: 1024 (order: 1, 8192 bytes) [ 2.372000] TCP: Hash tables configured (established 1024 bind 1024) [ 2.384000] TCP: reno registered [ 2.392000] UDP hash table entries: 256 (order: 1, 8192 bytes) [ 2.404000] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) [ 2.416000] NET: Registered protocol family 1 [ 2.424000] Load Kernel WDG Timer Module [ 2.432000] enable watchdog. [ 2.440000] Load Ralink Timer0 Module [ 2.448000] Load Ralink Timer2 Module [ 2.456000] squashfs: version 4.0 (2009/01/31) Phillip Lougher [ 2.468000] jffs2: version 2.2. (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc. [ 2.488000] msgmni has been set to 238 [ 2.496000] io scheduler noop registered (default) [ 2.504000] reg_int_mask=0, INT_MASK= 0 [ 2.512000] HSDMA_init [ 2.520000] [ 2.520000] hsdma_phy_tx_ring0 = 0x00c00000, hsdma_tx_ring0 = 0xa0c00000 [ 2.536000] [ 2.536000] hsdma_phy_rx_ring0 = 0x00c04000, hsdma_rx_ring0 = 0xa0c04000 [ 2.552000] TX_CTX_IDX0 = 0 [ 2.556000] TX_DTX_IDX0 = 0 [ 2.564000] RX_CRX_IDX0 = 3ff [ 2.568000] RX_DRX_IDX0 = 0 [ 2.576000] set_fe_HSDMA_glo_cfg [ 2.580000] HSDMA_GLO_CFG = 465 [ 2.592000] Serial: 8250/16550 driver, 2 ports, IRQ sharing enabled [ 2.604000] serial8250: ttyS0 at MMIO 0x1e000d00 (irq = 27) is a 16550A [ 2.620000] serial8250: ttyS1 at MMIO 0x1e000c00 (irq = 26) is a 16550A [ 2.632000] Ralink gpio driver initialized [ 2.640000] Enable Ralink GDMA Controller Module [ 2.652000] GDMA IP Version=3 [ 2.656000] flash manufacture id: c2, device id 20 18 [ 2.668000] MX25L12805D(c2 2018c220) (16384 Kbytes) [ 2.676000] mtd .name = raspi, .size = 0x01000000 (16M) .erasesize = 0x00010000 (64K) .numeraseregions = 0 [ 2.696000] 6 cmdlinepart partitions found on MTD device raspi [ 2.708000] Creating 6 MTD partitions on "raspi": [ 2.716000] 0x000000000000-0x000000050000 : "u-boot" [ 2.728000] 0x000000050000-0x000000060000 : "u-boot-env" [ 2.740000] 0x000000060000-0x000000070000 : "Factory" [ 2.752000] 0x000000070000-0x000000080000 : "product_info" [ 2.764000] 0x000000080000-0x000000090000 : "kdump" [ 2.776000] 0x000000090000-0x000001000000 : "firmware" [ 2.784000] 0x00000033522c-0x000001000000 : "rootfs" [ 2.796000] mtd: partition "rootfs" must either start or end on erase block boundary or be smaller than an erase block -- forcing read-only [ 2.820000] mtd: partition "rootfs_data" created automatically, ofs=0xb20000, len=0x4e0000 [ 2.840000] 0x000000b20000-0x000001000000 : "rootfs_data" [ 2.852000] register mt_drv [ 2.872000] [ 2.872000] == pAd = c0181000, size = 4868224, Status=0 == [ 2.884000] pAd->PciHif.CSRBaseAddress =0xc0080000, csr_addr=0xc0080000! [ 2.896000] RTMPInitPCIeDevice():device_id=0x7615 [ 2.908000] mt_pci_chip_cfg(): HWVer=0x8a10, FWVer=0x8a10, pAd->ChipID=0x7615 [ 2.920000] mt_pci_chip_cfg(): HIF_SYS_REV=0x76150001 [ 2.932000] AP Driver version-5.0.4.0 [ 2.940000] RtmpChipOpsHook(223): Not support for HIF_MT yet! MACVersion=0x0 [ 2.952000] mt7615_init()--> [ 2.960000] Use the default ePAeLNA bin image! [ 2.968000] Use the default /etc_ro/wlan/MT7615E_EEPROM1.bin bin image! [ 2.980000] <--mt7615_init() [ 2.988000] <-- RTMPAllocTxRxRingMemory, Status=0 [ 3.000000] [WASK][wask_init][354]Netlink WASK Module inserted. [ 3.012000] globalvar register success [ 3.020000] [WASK][wask_init][385]WASK NETLINK SUCCESS!!!!! [ 3.032000] ========STA INIT============= [ 3.040000] MTK NETLINK SUCCESS!!!!! [ 3.048000] Ralink APSoC Ethernet Driver Initilization. v3.1 1024 rx/tx descriptors allocated, mtu = 1500! [ 3.068000] PROC INIT OK! [ 3.072000] set CLK_CFG_0 = 0x40a00020!!!!!!!!!!!!!!!!!!1 [ 3.084000] hnat roaming work enable [ 3.100000] net eth0: loaded mt7621 driver [ 3.112000] Zhanguo debug ra2882eth_init : mt7530_probe successfully. [ 3.124000] TCP: cubic registered [ 3.132000] NET: Registered protocol family 10 [ 3.140000] NET: Registered protocol family 17 [ 3.148000] Bridge firewalling registered [ 3.156000] 8021q: 802.1Q VLAN Support v1.8 [ 3.172000] VFS: Mounted root (squashfs filesystem) readonly on device 31:6. [ 3.188000] Freeing unused kernel memory: 216K procd: Console is alive [ 4.136000] before nf_register_hooks [ 4.140000] insmod dns_ops ok! [ 4.148000] insmod br_dns_ops ok! procd: - preinit - [ 5.324000] Raeth v3.1 (Tasklet,SkbRecycle) [ 5.336000] phy_free_head is 0xc18000!!! [ 5.344000] phy_free_tail_phy is 0xc19ff0!!! [ 5.352000] txd_pool=a0c20000 phy_txd_pool=00C20000 [ 5.364000] ei_local->skb_free start address is 0x870fa6f4. [ 5.376000] free_txd: 00c20010, ei_local->cpu_ptr: 00C20000 [ 5.384000] POOL HEAD_PTR | DMA_PTR | CPU_PTR [ 5.396000] ----------------+---------+-------- [ 5.404000] 0xa0c20000 0x00C20000 0x00C20000 [ 5.412000] [ 5.412000] phy_qrx_ring = 0x00c1a000, qrx_ring = 0xa0c1a000 [ 5.428000] [ 5.428000] phy_rx_ring0 = 0x00c1c000, rx_ring[0] = 0xa0c1c000 [ 5.464000] MT7530 Reset Completed!! [ 5.476000] change HW-TRAP to 0x17c8f [ 5.488000] Ruijie change HW-TRAP to 0x17ccf [ 5.520000] GMAC1_MAC_ADRH -- : 0x0000ecb9 [ 5.528000] GMAC1_MAC_ADRL -- : 0x703262de [ 5.536000] CDMA_CSG_CFG = 81000000 [ 5.540000] GDMA1_FWD_CFG = 20710000 [ 5.548000] ====>>debug for 7530 resetIssue[WCNCR00205357], reg7d00 = 0x77775 mount_root. emmc_partition_find(0x703008, rootfs_data) (null) is not created by block2mtd, skip. jffs2 is ready No jffs2 marker was found [ 5.744000] jffs2: notice: (311) jffs2_build_xattr_subsystem: complete building xattr subsystem, 1 of xdatum (1 unchecked, 0 orphan) and 23 of xref (0 dead, 0 orphan) found. switching to overlay procd: - early - procd: - ubus - procd: - init - Please press Enter to activate this console. [ 11.472000] nf_conntrack version 0.5.0 (1911 buckets, 7644 max) [ 11.488000] [ 11.488000] rg_sys_info_sz:10 [ 11.496000] 0,creat name:manufacturer [ 11.504000] 1,creat name:oui [ 11.512000] 2,creat name:product_class [ 11.516000] 3,creat name:model [ 11.524000] 4,creat name:sys_mac [ 11.532000] 5,creat name:wan_ip [ 11.536000] 6,creat name:serial_num [ 11.544000] 7,creat name:hardware_version [ 11.552000] 8,creat name:software_version [ 11.560000] 9,creat name:product_id [ 11.568000] tun: Universal TUN/TAP device driver, 1.6 [ 11.580000] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> [ 11.596000] gre: GRE over IPv4 demultiplexor driver [ 11.608000] ip_gre: GRE over IPv4 tunneling driver [ 11.628000] ip6_tables: (C) 2000-2006 Netfilter Core Team [ 11.664000] NF register ebt rj to local module sucess! [ 11.676000] Netfilter messages via NETLINK v0.30. [ 11.688000] ip_set: protocol 6 [ 11.712000] u32 classifier [ 11.720000] input device check on [ 11.724000] Actions configured [ 11.748000] dev ra0 handler=8158c330, wdata= (null), ptr= (null) [ 11.760000] [ROAM_TUN_K] roam init sucess. [ 11.796000] Ebtables v2.0 registered [ 11.804000] ip_tables: (C) 2000-2006 Netfilter Core Team [ 11.816000] Type=Linux [ 11.968000] ps: can't get major 253 [ 12.056000] xt_time: kernel timezone is -0000 [ 12.084000] PPP generic driver version 2.4.2 [ 12.096000] PPP MPPE Compression module registered [ 12.108000] NET: Registered protocol family 24 [ 12.116000] PPTP driver version 0.8.5 [ 12.124000] ps: can't get major 253 [ 12.164000] ps: can't get major 253 [ 12.196000] ps: can't get major 253 [ 13.268000] mtdoops: Attached to MTD device 4 =============upinit_finished================ procd: - init complete -
==== OpenWrt bootlog ====
COPY HERE THE BOOTLOG ONCE OPENWRT IS INSTALLED AND RUNNING
===== Notes =====
Space for additional notes, links to forum threads or other resources.
* ...
===== Tags =====
Add tags below, then remove this fixme.