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toh:pcengines:apu2 [2018/04/16 21:07]
sebastian [Cryptographic hardware] added
toh:pcengines:apu2 [2018/09/20 17:05] (current)
jeff [PC Engines APU 2]
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 ====== PC Engines APU 2 ====== ====== PC Engines APU 2 ======
-The APU2 is a well built +The APU2 is a small [[docs:techref:​instructionset:​x86_64|x86_64]] single board computer. It will easily route/​packet filter a one Gigabit ​WAN. IPsec/VPN may drop that number a wee bit, the CPU has AES-NI acceleration,​ use AES-GCM for performance. 
-  * Quad core @ 1Ghz x64 SoC with 2-4 GB ECC RAM +Tested wifi options include the PC Engines supplied ​[[https://​pcengines.ch/​wle900vx.htm|WLE900VX]], ​[[https://​pcengines.ch/​wle600vx.htm|WLE600VX]] (both ath10k, ​802.11ac/​a/​b/​g/​n) and full feature support via [[https://​pcengines.ch/​wle200nx.htm|WLE200NX]] (ath9k, ​802.11a/​b/​g/​n) miniPCI express radio cards
-  * Three 1GigE Intel Ethernet and mini-PCIe slots +There are also board versions optimized for the usage of 3G / LTE modems, see [[toh:​pcengines:​apu3|PC Engines APU 3]].
-  * A phone SIM slot and mini-PCIe 3G/LTE modem support +
-  * mSATA (SSD) mini-PCIe and SD card slot +
-  * AMD-V / [[http://​www.cpu-world.com/​CPUs/​Puma/​AMD-G-Series%20GX-412TC.html|AMD Virtualization technology]] +
-  * Seventeen 3.3v GPIO pins and four UARTs! +
-It will easily route/​packet filter a 1 Gbit WAN. IPsec/VPN may drop that number a wee bit, the CPU has AES-NI acceleration,​ use AES-GCM for performance. +
-Tested wifi options include the PC Engines supplied [[https://​pcengines.ch/​wle600vx.htm|WLE600VX]]/​ath10k ​(802.11ac/​a/​b/​g/​n) and full feature support via [[https://​pcengines.ch/​wle200nx.htm|WLE200NX]]/​ath9k ​(802.11a/​b/​g/​n) miniPCI express radio cards.+
  
-APU system boards are designed and manufactured by [[http://pcengines.ch/apu2.htm|PC Engines]]. +APU system boards are designed and manufactured by PC Engines in Taiwan. 
-Boards are based on AMD Embedded G series GX-412TC low (6 to 12W) power consumption CPUs.+Boards are based on [[http://www.cpu-world.com/CPUs/​Puma/​AMD-G-Series%20GX-412TC.html|AMD Embedded G series GX-412TC]] low (6 to 12W) power consumption CPUs.
 APU boards and associated accessories are readily available from [[https://​pcengines.ch/​order.htm|resellers]] across Europe and North America. APU boards and associated accessories are readily available from [[https://​pcengines.ch/​order.htm|resellers]] across Europe and North America.
 +
 +<WRAP center round tip 60%>
 +There have been reports that "​old"​ SD cards with the 18.06.1 squashfs image are not recognized as bootable, though the ext4 image on the same card boots.
 +
 +2018-09 -- https://​forum.openwrt.org/​t/​sd-install-on-apu-2c2/​21584
 +</​WRAP>​
 +
 +
 +
 +===== Supported Versions =====
 +---- datatable ----
 +cols    : Brand, Model, Versions, Supported Current Rel, OEM device homepage URL_url, OWrt Forum Topic URL_url, Device Techdata_pageid
 +headers : Brand, Model, Version, Current Release, OEM Info, Forum Topic, Technical Data
 +align   : c,​c,​c,​c,​c,​c,​c
 +filter ​ : Brand=PC Engines
 +filter ​ : Model*~APU2
 +sort    : Model
 +----
 +
  
 ===== Hardware ===== ===== Hardware =====
 ---- datatable ---- ---- datatable ----
-cols    : Model, CPU, CPU Cores_, CPU MHZ, RAM MB, Ethernet Gbit ports_, Comments network ports_, USB ports_, Supported Since Rel, Supported Current Rel +cols    : Model, CPU, CPU Cores_, CPU MHZ, RAM MB, Ethernet Gbit ports_, Comments network ports_, USB ports_ 
-headers : Model, CPU, Cores, MHz, RAM, Gbit ports, NICs, USB, Supported since, Current Release+headers : Model, CPU, Cores, MHz, RAM, Gbit ports, NICs, USB
 align   : l,​c,​c,​c,​c,​c,​c,​c,​c,​c align   : l,​c,​c,​c,​c,​c,​c,​c,​c,​c
 filter ​ : Brand=PC Engines filter ​ : Brand=PC Engines
Line 24: Line 37:
 ---- ----
  
-  * CPU: AMD Embedded G series GX-412TC, 1 GHz quad Jaguar core with 64 bit and AES-NI support, 32K data + 32K instruction cache per core, shared 2MB L2 cache. 
-  * DRAM: 2 or 4 GB DDR3-1333 DRAM 
-  * Storage: Boot from m-SATA SSD, SD card (internal sdhci controller),​ or external USB. 1 SATA + power connector. 
-  * 12V DC, about 6 to 12W depending on CPU load. Jack = 2.5 mm, center positive 
-  * I/O: DB9 serial port, 2 USB 3.0 external + + 2 USB 2.0 internal, three front panel LEDs, pushbutton 
-  * Expansion: 2 miniPCI express (one with SIM socket), LPC bus, 17 GPIO headers, I2C bus 
-  * COM2 (3.3V RXD / TXD / RTS / DTR), COM3 and COM4 (3.3V DCD / DSR / RXD / RTS / TXD / CTS / DTR / GND) enabled via BIOS on [[https://​i.imgur.com/​assPwXR.png|the GPIO pins]]. 
-  * Board size: 6 x 6" (152.4 x 152.4 mm) - same as apu1d, alix2d13 and wrap1e. 
-  * Firmware: coreboot - [[https://​github.com/​pcengines/​coreboot|source]],​ [[https://​pcengines.github.io/​|releases]]. 
-  * Cooling: Conductive cooling from the CPU to the enclosure using a 3 mm alu heat spreader (included). 
  
-  * Datasheets[[https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/i211-ethernet-controller-datasheet.pdf|i211AT]], [[https://www.intel.com/content/dam/www/public/​us/​en/​documents/​datasheets/​i210-ethernet-controller-datasheet.pdf|i210AT]]+  * CPUAMD Embedded G series GX-412TC, 1 GHz quad Jaguar core with 64 bit and AES-NI support, 32K data + 32K instruction cache per core, shared 2MB L2 cache 
 +  * Currently (2018) one of the fastest performing SoCs running OpenWrt 
 +  * AMD-V (AMD hardware virtualization technology) 
 +  * DRAM2 or 4 GB DDR3-1333 DRAM 
 +  * mSATA (SSD) mini-PCIe and SD card slot 
 +  * Storage: Boot from m-SATA SSD, SD card (internal sdhci controller),​ or external USB. 1 SATA + power connector 
 +  * Power: 12V DC, about 6 to 12 W depending on CPU load. Jack = 2.5 mm, center positive 
 +  * I/O: DB9 serial port, 2 USB 3.0 external + 2 USB 2.0 (internal header), three front panel LEDs, pushbutton 
 +  * 2-3 1GigE Intel Ethernet and mini-PCIe slots 
 +  * A phone SIM slot and mini-PCIe 3G/LTE modem support 
 +  * Expansion: 2 miniPCI express (one with SIM socket), LPC bus, 17 GPIO headers (3.3v), I2C bus 
 +  * UART config: COM2 (3.3V RXD TXD RTS DTR), COM3 and COM4 (3.3V DCD DSR RXD RTS TXD CTS DTR / GND) enabled via BIOS on [[https://i.imgur.com/​assPwXR.png|the GPIO pins]] 
 +  * Board size: 6 x 6" (152.4 x 152.4 mm) - same as apu1dalix2d13 and wrap1e 
 +  * Firmware: Coreboot - [[https://github.com/pcengines/coreboot|source code]], [[https://pcengines.github.io/|releases]]
 +  * Cooling: An included 3 mm Aluminum heat spreader creates conductive cooling from the CPU to the enclosure and works quite well (50 C to 60 C). PC Engines tested the black enclosure to be a few degrees cooler
  
-==== Board schematics ​==== +==== Schematics and datasheets ​==== 
-For transparency,​ board schematics are available. This is a very nice initiative from PC Engines, which makes it a very good and long support board for OpenWrt: +  ​* ​PC Engines ​schematics: [[http://​www.pcengines.ch/​schema/​apu2c.pdf|APU2C]] 
-  * [[http://​www.pcengines.ch/​schema/​apu2c.pdf|PC Engines APU 2C* schematics]] +  * NIC Datasheets: ​[[https://www.intel.com/content/dam/​www/​public/​us/​en/​documents/​datasheets/​i211-ethernet-controller-datasheet.pdf|i211AT]], [[https://​www.intel.com/​content/​dam/​www/​public/​us/​en/​documents/​datasheets/​i210-ethernet-controller-datasheet.pdf|i210AT]]
-  * [[http://www.pcengines.ch/schema/apu3a.pdf|PC Engines APU 3A schematics]]+
  
 ==== Ethernet assignation apu2 ==== ==== Ethernet assignation apu2 ====
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 ==== Kernel modules ==== ==== Kernel modules ====
 The [[toh:​pcengines:​apu2#​generic_image|x86_64 images]] contain everything for basic operation and work out of the box on APU2 since release 17.01.2. The [[toh:​pcengines:​apu2#​generic_image|x86_64 images]] contain everything for basic operation and work out of the box on APU2 since release 17.01.2.
-Some modules for specific APU2 features are not included by default ​an can be installed using [[docs:​guide-user:​additional-software:​opkg|opkg]],​ or by including them in a custom build. ​+Some modules for specific APU2 features are not included by default ​and can be installed using [[docs:​guide-user:​additional-software:​opkg|opkg]],​ or by including them in a custom build. ​
  
 ^ Module(s) ​     ^ feature(s) ​     ^ menuconfig location ^ ^ Module(s) ​     ^ feature(s) ​     ^ menuconfig location ^
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 Other software packages may also be added to use certain APU2 featues: Other software packages may also be added to use certain APU2 featues:
 ^ Package(s) ​     ^ feature(s) ​     ^ menuconfig location ^ ^ Package(s) ​     ^ feature(s) ​     ^ menuconfig location ^
-| amd64-microcode | AMD CPU micricode ​| Firmware |+| amd64-microcode | AMD CPU microcode ​| Firmware |
 | flashrom | Tool to update APU BIOS | Utilities | | flashrom | Tool to update APU BIOS | Utilities |
 | irqbalance | IRQ usage balancing for multi-core systems | Utilities | | irqbalance | IRQ usage balancing for multi-core systems | Utilities |
Line 75: Line 91:
 The AMD GX-412TC supports the [[wp>AES instruction set|AES-NI instruction set]], which works without any kernel module or specific configuration. The AMD GX-412TC supports the [[wp>AES instruction set|AES-NI instruction set]], which works without any kernel module or specific configuration.
  
-The SoC also contains a cryptographic co-processor (AMD CCP), which requires ''​kmod-crypto-hw-ccp''​ to be installed. The CCP can be utilized to speed up various cryptographic algorithms in kernel space, like IPSec hashing for example. See [[docs:​techref:​hardware:​cryptographic.hardware.accelerators|Cryptographic Hardware Accelerators]] on how to enable ''/​dev/​crypto''​ and configure userspace libraries like OpenSSL to take advantage of it.+The SoC also contains a cryptographic co-processor (AMD CCP), which requires ''​kmod-crypto-hw-ccp''​ to be installed. The CCP can be utilized to speed up various cryptographic algorithms in kernel space, like IPSec hashing for example. See [[docs:​techref:​hardware:​cryptographic.hardware.accelerators|Cryptographic Hardware Accelerators]] on how to enable ''/​dev/​crypto''​ and configure userspace libraries like OpenSSL to take advantage of it. AES-GCM is currently the best security vs performance trade off. The APU2 is vulnerable to the recent AMD and Intel CPU security exploits.
  
 ===== Bootloader ===== ===== Bootloader =====
-APU boards use [[wp>​coreboot]]. The PC Engines BIOS firmware releases can be downloaded from [[https://​pcengines.github.io/​]],​ flashing instructions are located at the [[http://​pcengines.ch/​howto.htm#​bios|PCEngines HowTo section]].+APU boards use [[wp>​coreboot]]. The PC Engines BIOS firmware releases can be downloaded from [[https://​pcengines.github.io/​]],​ flashing instructions are located at the [[http://​pcengines.ch/​howto.htm#​bios|PCEngines HowTo section]]. ​Example ''​flashrom -w apu2_v4.6.8.rom -p internal''​
 There is also a [[https://​github.com/​pcengines/​apu2-documentation|documentation repository]] on github with information how to build and modify coreboot for APU boards. ​ There is also a [[https://​github.com/​pcengines/​apu2-documentation|documentation repository]] on github with information how to build and modify coreboot for APU boards. ​
  
Line 87: Line 103:
   * Standard Chaos Chalmer 15.05.1 won't boot from SD cards!   * Standard Chaos Chalmer 15.05.1 won't boot from SD cards!
   * Full support since LEDE-17.01.4   * Full support since LEDE-17.01.4
-  * See [[https://​github.com/​riptidewave93/​LEDE-APU2|LEDE-APU2 repository by riptidewave93]] for detailed configuration examples.+  * See [[https://​github.com/​riptidewave93/​LEDE-APU2|LEDE-APU2 repository ​/ closed Issues ​by riptidewave93]] for detailed configuration examples.
  
 ===== Installation ===== ===== Installation =====
  
 ==== Generic image ==== ==== Generic image ====
 +Images for x86 are provided with ext4 or squashfs. It's recommended to use squashfs. For more details read [[http://​lists.infradead.org/​pipermail/​lede-dev/​2018-April/​011803.html|this mailinglist thread]] and [[docs:​techref:​filesystems|Filesystems]]. See, however, warning at top of page on squashfs images not booting from "​old"​ SD cards.
 +
 +If you wish to write data to the same disk as OpenWrt is installed on, an ext4 filesystem with write persistence is useful. If using an SD card (as opposed to using an mSATA SSD or USB-attached SSD), the writable JFFS2 filesystem ​ has journaling and wear leveling may prolong SD card life. However, it will have to be built as OpenWrt does not auto-generate JFFS2 images. See [[https://​downloads.openwrt.org/​releases/​17.01.4/​targets/​x86/​64/​]]
  
 ---- datatable ---- ---- datatable ----
Line 101: Line 120:
 sort    : Model sort    : Model
 ---- ----
-Download ​a *combined-ext4.img.gz and write it to a SD-card or USB-Stick. Run ''​lsblk''​ to choose the correct device to write to.+ 
 +To install OpenWrt, download ​a *combined-squashfs.img[.gzand write it to a SD-card or USB-stick. Run ''​lsblk''​ to choose the correct device to write to. 
 +<​code>​ 
 +sudo dd status=progress bs=8M if=lede-17.01.4-x86-64-combined-squashfs.img of=/​dev/​sdX 
 +</​code>​ 
 +or
 <​code>​ <​code>​
-gzip -dc openwrt-x86-64-combined-ext4.img.gz | sudo dd status=progress bs=8M of=/dev/sdX+gzip -dc openwrt-x86-64-combined-squashfs.img.gz | sudo dd status=progress bs=8M of=/dev/sdX
 </​code>​ </​code>​
 +Boot the APU from the written stick/card.
  
 ==== Custom OpenWrt image ==== ==== Custom OpenWrt image ====
 +When building a custom image, choose target system x86, subtarget x86_64 and include desired [[toh:​pcengines:​apu2#​kernel_modules|APU-specific kernel modules]]. ​
 +It's possible to further optimize the produced binaries by generating instructions for AMD family 16h cores (march=btver2). Set ''​CONFIG_TARGET_OPTIMIZATION="​-Os -pipe -march=btver2"''​
  
-We are trying to compile with all optimization. This includes: +In menuconfig ​this option ​can be found at: 
-  * X86-64 architecture,​  +Advanced configuration options ​(for developers-> Target Options -> Target Optimizations
-  * AMD APU gcc optimization (this can boost performance around 50% on some applications),​ +
-  * SMP support ​(dual core),  +
-  * GPIO header support,  +
-  * LED support, and more.+
  
-Compile with X86_64 with APU GCC btver2 optimization.  +If you don't want to build from source, you can use the [[docs:guide-user:​additional-software:​imagebuilder|image builder]]
- +
-Here is a rather comprehensive ​[[https://​gist.github.com/​Strykar/​1fe4c236e15c63ccc0d335ba2c3d52be|sample .config file]]+
- +
-At present, we include the following feeds: +
-<​code>​ +
-./​scripts/​feeds install luci +
-</​code>​+
  
 ==== Configuration ==== ==== Configuration ====
  
 With the generic image, only the first port (eth0, the one close to the serial port) is active. ​ You should configure the other ports as appropriate. With the generic image, only the first port (eth0, the one close to the serial port) is active. ​ You should configure the other ports as appropriate.
 +
 +===== Sysupgrade =====
 +sysupgrade on x86 works with the same images as used for installation. Upload a *combined-squashfs.img.gz via LUCI or run
 +<​code>​
 +sysupgrade openwrt-x86-64-combined-squashfs.img.gz
 +</​code>​
  
 ===== Benchmark ===== ===== Benchmark =====
 +Teklager.se did a [[https://​teklager.se/​en/​knowledge-base/​compex-wle200nx-wle600vx-benchmark/​|Benchmark]] of two Compex wireless cards on pfSense and OpenWrt on an APU2C4. Quote from the article: //OpenWRT is just much better at wireless. It outperforms pfSense by almost 2x.//
  
-This benchmark is done with the generic x86 BB image (no SMP, i686). ​ One laptop is attached to eth0, and runs iperf towards a second laptop attached to eth1. 
  
 ===== Troubleshooting ===== ===== Troubleshooting =====
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 The SMBIOS board name entries differed in some releases of the coreboot 4.6.x cycle, the releases since v4.6.7 changed back to the old naming scheme. Since [[https://​git.openwrt.org/?​p=openwrt/​openwrt.git;​a=commit;​h=7e42cbaf2a1e40cfdd1abde876a1bb66db784420|commit 7e42cba]] both naming schemes are supported. The SMBIOS board name entries differed in some releases of the coreboot 4.6.x cycle, the releases since v4.6.7 changed back to the old naming scheme. Since [[https://​git.openwrt.org/?​p=openwrt/​openwrt.git;​a=commit;​h=7e42cbaf2a1e40cfdd1abde876a1bb66db784420|commit 7e42cba]] both naming schemes are supported.
 If LEDs aren't working, upgrade coreboot to at least v4.6.7 and/or install a current version of leds-apu2 which includes the mentioned commit. If LEDs aren't working, upgrade coreboot to at least v4.6.7 and/or install a current version of leds-apu2 which includes the mentioned commit.
 +
 +
 ===== Other Info ===== ===== Other Info =====
   * PC Engines support forum: [[http://​www.pcengines.info/​]]   * PC Engines support forum: [[http://​www.pcengines.info/​]]
   * PC Engines HowTo Pages: [[http://​pcengines.ch/​howto.htm]]   * PC Engines HowTo Pages: [[http://​pcengines.ch/​howto.htm]]
 +
  
 ===== Tags ===== ===== Tags =====
 {{tag>​x86 x86-64 apu apu2 PCEngines devBoard coreboot 0WNIC GigabitEthernet no_switch 12v_powered}} {{tag>​x86 x86-64 apu apu2 PCEngines devBoard coreboot 0WNIC GigabitEthernet no_switch 12v_powered}}
toh/pcengines/apu2.1523912853.txt.gz · Last modified: 2018/04/16 21:07 by sebastian