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toh:d-link:dir-853_a1 [2024/02/13 04:02] – [Flash Layout] rikka0w0toh:d-link:dir-853_a1 [2024/02/13 05:05] – [Hardware mods] rikka0w0
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 {{media:dlink:dir-853_a1:back.png|Back}} {{media:dlink:dir-853_a1:back.png|Back}}
  
-===== Supported Versions =====+ 
 +===== Hardware Highlights =====
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-===== Hardware Highlights =====+ 
 +===== Supported Versions =====
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- 
-===== Installation ===== 
 <!-- ToH: { <!-- ToH: {
   "source": "json",   "source": "json",
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 } --> } -->
  
-  - Open the case, and solder the 4-pin header near the WAN port. 
-  - Connect it to a USB-UART TTL (3.3V) adapter, no need to connect VCC. 
-  - Open a terminal emulator (e.g. screen /dev/ttyUSB0 on linux) with the settings mentioned above. 
-  - Setup a TFTP server on your PC that can serve xxx-ramips-mt7621-dlink_dir-853-a1-initramfs-kernel.bin. 
-  - Connect any LAN port to your PC and set a static IPv4 address to 192.168.0.101 (netmask 255.255.255.0). 
-  - Power on the device and keeps pressing 1 until you see the prompt. 
-  - Use default IP addresses and enter the file name accordingly, then hit enter. 
-  - Wait until it boots to OpenWrt, the default IP address is 192.168.1.1, you need to change your PC network adapter to use DHCP in order to access LUCI. 
-  - So far, the OpenWrt runs in RAM and the flash contents are not touched. You can try OpenWrt without having to overwrite the stock firmware, a reboot clears all changes. 
-  - Optionally, backup the stock firmware (the "firmware" partition) in Luci. 
-  - To permantly install OpenWrt to the device , click on "System -> Backup/Flash Firmware" in Luci and flash xxx-ramips-mt7621-dlink_dir-853-a1-squashfs-sysupgrade.bin 
  
 ==== OEM easy installation ==== ==== OEM easy installation ====
 It is possible to install OpenWrt from the stock web interface without having to open the case of the router. [[docs:guide-user:installation:recovery_methods:d-link_recovery_gui#about_encrypted_firmwares|Since 2018, D-Link added encryption to its firmware files and the stock web interface only accepts encrypted and valid firmware.]] It is possible to install OpenWrt from the stock web interface without having to open the case of the router. [[docs:guide-user:installation:recovery_methods:d-link_recovery_gui#about_encrypted_firmwares|Since 2018, D-Link added encryption to its firmware files and the stock web interface only accepts encrypted and valid firmware.]]
  
-You would need the imgcrypt tool to encrypt a OpenWrt factory binary file so that the stock web interface accepts it:+**To walk around that and ease the installation of OpenWrt, first install this encrypted OpenWrt image (become dated), and then upgrade (using Luci Sysupgrade) to the latest OpenWrt:** 
 + 
 +https://github.com/openwrt/openwrt/files/10833430/dir-853-a1-fac-enc.bin.zip 
 + 
 +The above image was generated by the imgcrypt encryption tool from an official OpenWrt factory image:
 <code> <code>
 ./imgcrypt openwrt-ramips-mt7621-dlink_dir-853-a1-squashfs-factory.bin dir-853-a1-fac-enc.bin ./imgcrypt openwrt-ramips-mt7621-dlink_dir-853-a1-squashfs-factory.bin dir-853-a1-fac-enc.bin
Line 61: Line 54:
  
 The imgcrypt tool is only available in source code at https://dlink-gpl.s3.amazonaws.com/GPL1700193/DIR853A2_V1.00B03.tar.gz. The imgcrypt tool is only available in source code at https://dlink-gpl.s3.amazonaws.com/GPL1700193/DIR853A2_V1.00B03.tar.gz.
 +
 You need to compile it on a 32-bit Linux or add 32-bit support to your AMD64 Linux distro. You need to compile it on a 32-bit Linux or add 32-bit support to your AMD64 Linux distro.
 +
  
 See: See:
 https://forum.openwrt.org/t/re-dir-853-a2/152308/18?u=rikka0w0 https://forum.openwrt.org/t/re-dir-853-a2/152308/18?u=rikka0w0
  
 +https://github.com/openwrt/openwrt/pull/12087
 +
 +===== Basic configuration =====
 +-> [[docs:guide-user:base-system:start|Basic configuration]] After flashing, proceed with this.\\
 +
 +Known problems:
 +
 +  * WLAN0 defaults to 5G after a fresh installation, to enable 2.4G network, you need to config it manually in LUCI.
 +  * If you see jffs2 related warnings/errors after updating from the stock web interface, you need to do a reset in LUCI. The error will be gone after a cold reboot.
 +
 +
 +==== OEM installation and Debricking using the serial TFTP method ====
 +
 +->  [[docs:guide-user:installation:generic.flashing.tftp]]
 +
 +-> [[docs:guide-user:troubleshooting:generic.debrick]]
 +
 +__Opening the case of the router may avoid its warranty. You may only consider this approach if you familiar with soldering. Otherwise, please proceed to **OEM easy installation**.__
 +
 +In this method, we first load an OpenWrt image into the RAM from the stock U-boot serial interface, then we install OpenWrt permanently to the flash.
 +
 +  - Open the case, and solder the 4-pin header near the WAN port.
 +  - Connect it to a USB-UART TTL (3.3V) adapter, no need to connect VCC.
 +  - Open a terminal emulator (e.g. ''screen /dev/ttyUSB0'' on linux, or [[https://putty.org/]] on Windows) with 57600 8N1.
 +  - Setup a TFTP server on your PC that can serve ''xxx-ramips-mt7621-dlink_dir-853-a1-initramfs-kernel.bin''.
 +  - Connect any LAN port to your PC and set a static IPv4 address to ''192.168.0.101'' (netmask ''255.255.255.0'').
 +  - Power on the device and keeps pressing 1 until you see the prompt.
 +  - Use default IP addresses and enter the file name accordingly, then hit enter.
 +  - Wait until it boots to OpenWrt, the default IP address is ''192.168.1.1'', you need to change your PC network adapter to use DHCP in order to access LUCI.
 +  - **So far, the OpenWrt runs in RAM and the flash contents are not touched.** You can try OpenWrt without having to overwrite the stock firmware, a reboot clears all changes.
 +  - Optionally, backup the stock firmware (the "firmware" partition) in Luci.
 +  - To permantly install OpenWrt to the device , click on "System -> Backup/Flash Firmware" in Luci and flash ''xxx-ramips-mt7621-dlink_dir-853-a1-squashfs-sysupgrade.bin''
 +
 +Note:
 +
 +**You should never flash images named ''xxx-initramfs-kernel.bin'' to the flash!**
  
 ===== Flash Layout ===== ===== Flash Layout =====
Line 83: Line 114:
 0x000000fb0000-0x000001000000 : "Private" 0x000000fb0000-0x000001000000 : "Private"
 </code> </code>
 +
  
 OpenWrt: OpenWrt:
Line 102: Line 134:
 | :::                                  :::                                                            |  :::                              :::                          |  :::                                |  :::                              |  ''/'' as OverlayFS, **rw**                                         | :::                                  | | :::                                  :::                                                            |  :::                              :::                          |  :::                                |  :::                              |  ''/'' as OverlayFS, **rw**                                         | :::                                  |
  
-==== OEM installation using the TFTP method ==== 
- 
-->  [[docs:guide-user:installation:generic.flashing.tftp]] 
- 
-=== Specific values needed for tftp === 
- 
-<WRAP BOX> 
- 
-FIXME Enter values for "FILL-IN" below 
- 
-^ Bootloader tftp server IPv4 address  | FILL-IN   | 
-^ Bootloader MAC address (special)     | FILL-IN   | 
-^ Firmware tftp image                  | [[:downloads|Latest OpenWrt release]] (**''NOTE:''** Name must contain //"tftp"//) | 
-^ TFTP transfer window                 | FILL-IN seconds                                | 
-^ TFTP window start                    | approximately FILL-IN seconds after power on   | 
-^ TFTP client required IP address      | FILL-IN                                        | 
- 
-</WRAP> 
  
 ===== Upgrading OpenWrt ===== ===== Upgrading OpenWrt =====
 ->  [[docs:guide-user:installation:generic.sysupgrade]] ->  [[docs:guide-user:installation:generic.sysupgrade]]
  
-<WRAP BOX> +Both LuCI web upgrade and terminal upgrade works.
- +
-FIXME These are generic instructions. Update with your router's specifics. +
- +
-==== LuCI Web Upgrade Process ==== +
- +
-  * Browse to ''<nowiki>http://192.168.1.1/cgi-bin/luci/mini/system/upgrade/</nowiki>'' LuCI Upgrade URL +
-  * Upload image file for sysupgrade to LuCI +
-  * Wait for reboot +
- +
-==== Terminal Upgrade Process ==== +
- +
-If you don't have a GUI (LuCI) available, you can alternatively upgrade via the command line. +
-There are two command line methods for upgrading: +
- +
-  * ''sysupgrade'' +
-  * ''mtd'' +
- +
-Note: It is important that you put the firmware image into the ramdisk (/tmp) before you start flashing. +
- +
-=== sysupgrade === +
- +
-  * Login as root via SSH on 192.168.1.1, then enter the following commands: +
- +
-<code> +
-cd /tmp +
-wget http://downloads.openwrt.org/snapshots/trunk/XXX/xxx.abc +
-sysupgrade /tmp/xxx.abc +
-</code> +
- +
-=== mtd === +
- +
-If ''sysupgrade'' does not support this router, use ''mtd''+
- +
-  * Login as root via SSH on 192.168.1.1, then enter the following commands: +
- +
-<code> +
-cd /tmp +
-wget http://downloads.openwrt.org/snapshots/trunk/XXX/xxx.abc +
-mtd write /tmp/xxx.abc linux && reboot +
-</code> +
- +
-</WRAP> +
- +
-===== Debricking ===== +
--> [[docs:guide-user:troubleshooting:generic.debrick]]+
  
 ===== Failsafe mode ===== ===== Failsafe mode =====
 -> [[docs:guide-user:troubleshooting:failsafe_and_factory_reset]] -> [[docs:guide-user:troubleshooting:failsafe_and_factory_reset]]
  
-===== Basic configuration ===== 
--> [[docs:guide-user:base-system:start|Basic configuration]] After flashing, proceed with this.\\ 
-Set up your Internet connection, configure wireless, configure USB port, etc. 
  
-===== Specific Configuration ===== 
  
-<WRAP BOX> +===== Hardware ===== 
-FIXME Please fill in real values for this device, then remove the EXAMPLEs+==== MAC addresses on OEM firmware ==== 
 +^ Interface Name   ^ Location on the flash ^ Note    ^ 
 +| lan (eth2)       | @factory + 0xe000     | on label   | 
 +| wan (eth3)       | @factory + 0xe006                | 
 +| 2.4g (rax0)      | not on flash          | lan + 1    | 
 +| 5g (ra0)         | not on flash          | lan + 2    |
  
-==== Network interfaces ==== +==== Info ====
-The default network configuration is: +
-^ Interface Name   ^ Description                  ^ Default configuration    ^ +
-| br-lan           | EXAMPLE LAN & WiFi           | EXAMPLE 192.168.1.1/24   | +
-| vlan0 (eth0.0)   | EXAMPLE LAN ports (1 to 4)   | EXAMPLE None             | +
-| vlan1 (eth0.1)   | EXAMPLE WAN port             | EXAMPLE DHCP             | +
-| wl0              | EXAMPLE WiFi                 | EXAMPLE Disabled         |+
  
-</WRAP>+  * LEDs: Power Blue+Orange,Wan Blue+Orange,WPS Blue,"2.4G"Blue, "5G" Blue, USB Blue 
 +  * Buttons: Reset,WPS, Wifi
  
-==== Switch Ports (for VLANs) ==== 
-<WRAP BOX> 
-FIXME Please fill in real values for this device, then remove the EXAMPLEs 
- 
-Numbers 0-3 are Ports 1-4 as labeled on the unit, number 4 is the Internet (WAN) on the unit, 5 is the internal connection to the router itself. Don't be fooled: Port 1 on the unit is number 3 when configuring VLANs. vlan0 = eth0.0, vlan1 = eth0.1 and so on. 
-^ Port             ^ Switch port   ^ 
-| Internet (WAN)   | EXAMPLE 4     | 
-| LAN 1            | EXAMPLE 3     | 
-| LAN 2            | EXAMPLE 2     | 
-| LAN 3            | EXAMPLE 1     | 
-| LAN 4            | EXAMPLE 0     | 
- 
-</WRAP> 
- 
-==== Buttons ==== 
--> [[docs:guide-user:hardware:hardware.button]] on howto use and configure the hardware button(s). 
-Here, we merely name the buttons, so we can use them in the above Howto. 
- 
-<WRAP BOX> 
-FIXME Please fill in real values for this device, then remove the EXAMPLEs 
- 
-The D-Link DIR-853 has the following buttons: 
- 
-^ BUTTON                       ^ Event   ^ 
-| EXAMPLE Reset                |  reset  | 
-| EXAMPLE Secure Easy Setup    |   ses   | 
-| EXAMPLE No buttons at all.      -    | 
- 
-</WRAP> 
- 
-===== Hardware ===== 
-==== Info ==== 
 <WRAP BOX> <WRAP BOX>
 FIXME FIXME
Line 242: Line 175:
 ---- ----
  
-==== Photos ==== 
-/* =====>>>>> Standard size for photos: add ?400 to the medialink                                */ 
-/* When uploading photos, **name them** intelligently. Nobody knows what 20100930_000602.jpg is! */ 
-/* e.g. {{:media:yourbrand:yourbrand_yourmodel_front.jpg?400|}}                                  */ 
-/* Thanks, your wiki administration - Oct. 2015 */ 
  
-//Front://\\ +==== Opening the case ====
-**Insert photo of front of the casing**+
  
-//Back://\\ +Remove four screws on the bottom of the device. No adhesive.
-**Insert photo of back of the casing** +
- +
-//Backside label://\\ +
-**Insert photo of backside label** +
- +
-==== Opening the case ====+
  
 **Note:** This will void your warranty! **Note:** This will void your warranty!
- 
-<WRAP BOX> 
-FIXME //Describe what needs to be done to open the device, e.g. remove rubber feet, adhesive labels, screws, ...// 
-  * To remove the cover and open the device, do a/b/c 
-</WRAP> 
  
 //Main PCB://\\ //Main PCB://\\
-**Insert photo of PCB** +{{media:dlink:dir-853_a1:internal.jpg}}
 ==== Serial ==== ==== Serial ====
 -> [[docs:techref:hardware:port.serial]] general information about the serial port, serial port cable, etc. -> [[docs:techref:hardware:port.serial]] general information about the serial port, serial port cable, etc.
  
-How to connect to the Serial Port of this specific device:\\ +The serial header locate near the power jack and it is not populated by default. Soldering is necessary.
-**Insert photo of PCB with markings for serial port**+
  
-<WRAP BOX> +^ Serial connection parameters\\ for D-Link DIR-853 A1 | 57600, 8N1, 3.3V |
-FIXME //Replace EXAMPLE by real values.// +
-</WRAP>+
  
-^ Serial connection parameters\\ for D-Link DIR-853 A1 | EXAMPLE 115200, 8N1, 3.3V |+There is no need to connect Vcc to an external 3.3V.
  
-==== JTAG ==== +{{media:dlink:dir-853_a1:serial.png}}
--> [[docs:techref:hardware:port.jtag]] general information about the JTAG port, JTAG cable, etc. +
- +
-How to connect to the JTAG Port of this specific device:\\ +
-**Insert photo of PCB with markings for JTAG port**+
  
 ===== Bootloader mods ===== ===== Bootloader mods =====
Line 292: Line 200:
 ===== Hardware mods ===== ===== Hardware mods =====
  
-None so far.+**Not verified!** 
 + 
 +There is an unpopulated USB 2.0 port on the PCB. To use it, you need to short circuit R31, LB15, R35, R38, and R37 on the PCB: 
 + 
 +{{media:dlink:dir-853_a1:usb_mod.jpg}} 
 + 
 +The pin out of the USB socket (from the top to bottom) is: 
 +  - Vcc, 5V 
 +  - D- 
 +  - D+ 
 +  - GND 
 + 
 +This port should work on the official OpenWrt firmware, as ''mt7621.dtsi'' suggests that it is enabled by default.
  
  
Line 303: Line 223:
 ==== OpenWrt bootlog ==== ==== OpenWrt bootlog ====
 <WRAP bootlog> <WRAP bootlog>
-<nowiki>COPY HERE THE BOOTLOG ONCE OPENWRT IS INSTALLED AND RUNNING</nowiki>+<nowiki>=================================================================== 
 +                MT7621   stage1 code 10:33:55 (ASIC) 
 +                CPU=500000000 HZ BUS=166666666 HZ 
 +================================================================== 
 +Change MPLL source from XTAL to CR... 
 +do MEMPLL setting.. 
 +MEMPLL Config : 0x11100000 
 +3PLL mode + External loopback 
 +=== XTAL-40Mhz === DDR-1200Mhz === 
 +PLL4 FB_DL: 0x6, 1/0 = 580/444 19000000 
 +PLL2 FB_DL: 0x10, 1/0 = 563/461 41000000 
 +PLL3 FB_DL: 0x11, 1/0 = 587/437 45000000 
 +do DDR setting..[01F40000] 
 +Apply DDR3 Setting...(use customer AC) 
 +          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120 
 +      -------------------------------------------------------------------------------- 
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 +0017:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
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 +001B:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001C:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001D:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001E:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001F:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +rank 0 coarse = 15 
 +rank 0 fine = 72 
 +B:|    0    0    0    0    0    0    0    0    1    1    1    0    0    0    0    0 
 +opt_dle value:9 
 +DRAMC_R0DELDLY[018]=00001F20 
 +================================================================== 
 +                RX      DQS perbit delay software calibration 
 +================================================================== 
 +1.0-15 bit dq delay value 
 +================================================================== 
 +bit|      1  2  3  4  5  6  7  8  9 
 +-------------------------------------- 
 +0 |    10 10 10 11 8 9 10 7 7 8 
 +10 |    9 9 9 10 9 10 
 +-------------------------------------- 
 + 
 +================================================================== 
 +2.dqs window 
 +x=pass dqs delay value (min~max)center 
 +y=0-7bit DQ of every group 
 +input delay:DQS0 =32 DQS1 = 31 
 +================================================================== 
 +bit     DQS0     bit      DQS1 
 +0  (1~62)31  8  (1~58)29 
 +1  (1~64)32  9  (1~60)30 
 +2  (1~60)30  10  (1~62)31 
 +3  (1~62)31  11  (0~57)28 
 +4  (1~60)30  12  (1~60)30 
 +5  (1~64)32  13  (1~60)30 
 +6  (1~62)31  14  (1~62)31 
 +7  (1~64)32  15  (1~61)31 
 +================================================================== 
 +3.dq delay value last 
 +================================================================== 
 +bit|    0  1  2  3  4  5  6  7  8   9 
 +-------------------------------------- 
 +0 |    11 10 12 12 10 9 11 7 9 9 
 +10 |    9 12 10 11 9 10 
 +================================================================== 
 +================================================================== 
 +     TX  perbyte calibration 
 +================================================================== 
 +DQS loop = 15, cmp_err_1 = ffff0000 
 +dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1 
 +dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2 
 +DQ loop=15, cmp_err_1 = ffff00a0 
 +dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=1 
 +DQ loop=14, cmp_err_1 = ffff0080 
 +DQ loop=13, cmp_err_1 = ffff0000 
 +dqs_perbyte_dly.last_dqdly_pass[0]=13,  finish count=2 
 +byte:0, (DQS,DQ)=(9,8) 
 +byte:1, (DQS,DQ)=(8,8) 
 +20,data:89 
 +[EMI] DRAMC calibration passed 
 + 
 +=================================================================== 
 +                MT7621   stage1 code done 
 +                CPU=500000000 HZ BUS=166666666 HZ 
 +=================================================================== 
 + 
 + 
 +U-Boot 1.1.3 (Jun 27 2019 - 20:25:37) 
 + 
 +Board: Ralink APSoC DRAM:  128 MB 
 +relocate_code Pointer at: 87fa8000 
 + 
 +Config XHCI 40M PLL 
 +****************************** 
 +Software System Reset Occurred 
 +****************************** 
 +flash manufacture id: c8, device id 40 18 
 +find flash: GD25Q128C 
 +============================================ 
 +Ralink UBoot Version: 5.0.0.0 
 +-------------------------------------------- 
 +ASIC MT7621A DualCore (MAC to MT7530 Mode) 
 +DRAM_CONF_FROM: Auto-Detection 
 +DRAM_TYPE: DDR3 
 +DRAM bus: 16 bit 
 +Xtal Mode=3 OCP Ratio=1/3 
 +Flash component: SPI Flash 
 +Date:Jun 27 2019  Time:20:25:37 
 +============================================ 
 +icache: sets:256, ways:4, linesz:32 ,total:32768 
 +dcache: sets:256, ways:4, linesz:32 ,total:32768 
 + 
 + ##### The CPU freq = 880 MHZ #### 
 + estimate memory size =128 Mbytes 
 +#Reset_MT7530 
 +set LAN/WAN LLLLW 
 +########RESET_GPIO_NUM:
 + 
 +Please choose the operation: 
 +   1: Load system code to SDRAM via TFTP. 
 +   2: Load system code then write to Flash via TFTP. 
 +   3: Boot system code via Flash (default). 
 +   4: Entr boot command line interface. 
 +   6: System Enter UBoot to Update Img or Bin. 
 +   7: Load Boot Loader code then write to Flash via Serial. 
 +   9: Load Boot Loader code then write to Flash via TFTP. 
 +default: 3                                                                                                                                                                                                                                 0 
 + 
 +3: System Boot system code via Flash. 
 +## Booting image at bc060000 ... 
 +   Image Name:   MIPS OpenWrt Linux-5.10.146 
 +   Image Type:   MIPS Linux Kernel Image (lzma compressed) 
 +   Data Size:    2708134 Bytes =  2.6 MB 
 +   Load Address: 80001000 
 +   Entry Point:  80001000 
 +   Verifying Checksum ... OK 
 +   Uncompressing Kernel Image ... OK 
 +No initrd 
 +## Transferring control to Linux (at address 80001000) ... 
 +## Giving linux memsize in MB, 128 
 + 
 +Starting kernel ... 
 + 
 +[    0.000000] Linux version 5.10.146 (builder@buildhost) (mipsel-openwrt-linux-musl-gcc (OpenWrt GCC 11.2.0 r19803-9a599fee93) 11.2.0, GNU ld (GNU Binutils) 2.37) #0 SMP Fri Oct 14 22:44:41 2022 
 +[    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3 
 +[    0.000000] printk: bootconsole [early0] enabled 
 +[    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc) 
 +[    0.000000] MIPS: machine is D-Link DIR-853 A1 
 +[    0.000000] Initrd not found or empty - disabling initrd 
 +[    0.000000] VPE topology {2,2} total 4 
 +[    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. 
 +[    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes 
 +[    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. 
 +[    0.000000] Zone ranges: 
 +[    0.000000]   Normal   [mem 0x0000000000000000-0x0000000007ffffff] 
 +[    0.000000]   HighMem  empty 
 +[    0.000000] Movable zone start for each node 
 +[    0.000000] Early memory node ranges 
 +[    0.000000]   node   0: [mem 0x0000000000000000-0x0000000007ffffff] 
 +[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff] 
 +[    0.000000] percpu: Embedded 15 pages/cpu s30256 r8192 d22992 u61440 
 +[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32480 
 +[    0.000000] Kernel command line: console=ttyS0,57600 rootfstype=squashfs,jffs2 
 +[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear) 
 +[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear) 
 +[    0.000000] Writing ErrCtl register=00016080 
 +[    0.000000] Readback ErrCtl register=00016080 
 +[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off 
 +[    0.000000] Memory: 119472K/131072K available (7026K kernel code, 631K rwdata, 828K rodata, 1292K init, 243K bss, 11600K reserved, 0K cma-reserved, 0K highmem) 
 +[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 
 +[    0.000000] rcu: Hierarchical RCU implementation. 
 +[    0.000000]  Tracing variant of Tasks RCU enabled. 
 +[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. 
 +[    0.000000] NR_IRQS: 256 
 +[    0.000000] CPU Clock: 880MHz 
 +[    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcaf478abb4, max_idle_ns: 440795247997 ns 
 +[    0.000013] sched_clock: 64 bits at 880MHz, resolution 1ns, wraps every 4398046511103ns 
 +[    0.015853] clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 4343773742 ns 
 +[    0.033805] Calibrating delay loop... 586.13 BogoMIPS (lpj=2930688) 
 +[    0.106122] pid_max: default: 32768 minimum: 301 
 +[    0.115430] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) 
 +[    0.129834] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) 
 +[    0.148078] rcu: Hierarchical SRCU implementation. 
 +[    0.157881] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build 
 +[    0.173444] smp: Bringing up secondary CPUs ... 
 +[    0.183187] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. 
 +[    0.183197] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes 
 +[    0.183209] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. 
 +[    0.183284] CPU1 revision is: 0001992f (MIPS 1004Kc) 
 +[    0.243287] Synchronize counters for CPU 1: done. 
 +[    0.305407] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. 
 +[    0.305417] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes 
 +[    0.305425] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. 
 +[    0.305473] CPU2 revision is: 0001992f (MIPS 1004Kc) 
 +[    0.364384] Synchronize counters for CPU 2: done. 
 +[    0.424710] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. 
 +[    0.424719] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes 
 +[    0.424728] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. 
 +[    0.424781] CPU3 revision is: 0001992f (MIPS 1004Kc) 
 +[    0.483959] Synchronize counters for CPU 3: done. 
 +[    0.543570] smp: Brought up 1 node, 4 CPUs 
 +[    0.555778] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns 
 +[    0.575280] futex hash table entries: 1024 (order: 3, 32768 bytes, linear) 
 +[    0.589099] pinctrl core: initialized pinctrl subsystem 
 +[    0.601798] NET: Registered protocol family 16 
 +[    0.611696] thermal_sys: Registered thermal governor 'step_wise' 
 +[    0.613145] cpuidle: using governor teo 
 +[    0.671207] clocksource: Switched to clocksource GIC 
 +[    0.682995] NET: Registered protocol family 2 
 +[    0.691984] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear) 
 +[    0.707203] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear) 
 +[    0.723831] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear) 
 +[    0.739004] TCP bind hash table entries: 1024 (order: 1, 8192 bytes, linear) 
 +[    0.752943] TCP: Hash tables configured (established 1024 bind 1024) 
 +[    0.765714] UDP hash table entries: 256 (order: 1, 8192 bytes, linear) 
 +[    0.778604] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear) 
 +[    0.792725] NET: Registered protocol family 1 
 +[    0.801309] PCI: CLS 0 bytes, default 32 
 +[    0.811464] workingset: timestamp_bits=14 max_order=15 bucket_order=1 
 +[    0.828391] squashfs: version 4.0 (2009/01/31) Phillip Lougher 
 +[    0.839898] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc. 
 +[    0.860175] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251) 
 +[    0.876552] mt7621_gpio 1e000600.gpio: registering 32 gpios 
 +[    0.887905] mt7621_gpio 1e000600.gpio: registering 32 gpios 
 +[    0.899236] mt7621_gpio 1e000600.gpio: registering 32 gpios 
 +[    0.911221] Serial: 8250/16550 driver, 16 ports, IRQ sharing enabled 
 +[    0.928100] printk: console [ttyS0] disabled 
 +[    0.936579] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 19, base_baud = 3125000) is a 16550A 
 +[    0.954502] printk: console [ttyS0] enabled 
 +[    0.954502] printk: console [ttyS0] enabled 
 +[    0.971027] printk: bootconsole [early0] disabled 
 +[    0.971027] printk: bootconsole [early0] disabled 
 +[    0.992973] spi-mt7621 1e000b00.spi: sys_freq: 220000000 
 +[    1.005150] spi-nor spi0.0: gd25q128 (16384 Kbytes) 
 +[    1.014989] 6 fixed-partitions partitions found on MTD device spi0.0 
 +[    1.027693] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 
 +[    1.042271] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 
 +[    1.057656] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 
 +[    1.072275] OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 
 +[    1.087061] Creating 6 MTD partitions on "spi0.0": 
 +[    1.096617] 0x000000000000-0x000000030000 : "u-boot" 
 +[    1.107509] 0x000000030000-0x000000040000 : "u-boot-env" 
 +[    1.119251] 0x000000040000-0x000000050000 : "factory" 
 +[    1.130404] 0x000000050000-0x000000060000 : "config2_stock" 
 +[    1.142841] 0x000000060000-0x000000fb0000 : "firmware" 
 +[    1.154222] 2 uimage-fw partitions found on MTD device firmware 
 +[    1.166043] Creating 2 MTD partitions on "firmware": 
 +[    1.175933] 0x000000000000-0x000000295346 : "kernel" 
 +[    1.185842] mtd: partition "kernel" doesn't end on an erase/write block -- force read-only 
 +[    1.203361] 0x000000295346-0x000000f50000 : "rootfs" 
 +[    1.213272] mtd: partition "rootfs" doesn't start on an erase/write block boundary -- force read-only 
 +[    1.232457] mtd: device 6 (rootfs) set to be root filesystem 
 +[    1.243867] 1 squashfs-split partitions found on MTD device rootfs 
 +[    1.256181] 0x0000006c0000-0x000000f50000 : "rootfs_data" 
 +[    1.267905] 0x000000fb0000-0x000001000000 : "private_stock" 
 +[    1.322403] mt7530 mdio-bus:1f: MT7530 adapts as multi-chip module 
 +[    1.339352] mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 21 
 +[    1.357067] mtk_soc_eth 1e100000.ethernet wan: mediatek frame engine at 0xbe100000, irq 21 
 +[    1.374602] i2c /dev entries driver 
 +[    1.384253] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges: 
 +[    1.397659] mt7621-pci 1e140000.pcie:   No bus range found for /pcie@1e140000, using [bus 00-ff] 
 +[    1.415203] mt7621-pci 1e140000.pcie:      MEM 0x0060000000..0x006fffffff -> 0x0000000000 
 +[    1.431507] mt7621-pci 1e140000.pcie:       IO 0x001e160000..0x001e16ffff -> 0x0000000000 
 +[    1.447886] mt7621-pci 1e140000.pcie: Parsing DT failed 
 +[    1.460516] NET: Registered protocol family 10 
 +[    1.471303] Segment Routing with IPv6 
 +[    1.478696] NET: Registered protocol family 17 
 +[    1.487665] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this. 
 +[    1.513867] 8021q: 802.1Q VLAN Support v1.8 
 +[    1.525571] mt7530 mdio-bus:1f: MT7530 adapts as multi-chip module 
 +[    1.554143] mt7530 mdio-bus:1f lan4 (uninitialized): PHY [mt7530-0:00] driver [MediaTek MT7530 PHY] (irq=26) 
 +[    1.576200] mt7530 mdio-bus:1f lan3 (uninitialized): PHY [mt7530-0:01] driver [MediaTek MT7530 PHY] (irq=27) 
 +[    1.598237] mt7530 mdio-bus:1f lan2 (uninitialized): PHY [mt7530-0:02] driver [MediaTek MT7530 PHY] (irq=28) 
 +[    1.620329] mt7530 mdio-bus:1f lan1 (uninitialized): PHY [mt7530-0:03] driver [MediaTek MT7530 PHY] (irq=29) 
 +[    1.643277] mt7530 mdio-bus:1f: configuring for fixed/rgmii link mode 
 +[    1.660099] DSA: tree 0 setup 
 +[    1.666369] rt2880-pinmux pinctrl: pcie is already enabled 
 +[    1.677406] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges: 
 +[    1.690785] mt7621-pci 1e140000.pcie:   No bus range found for /pcie@1e140000, using [bus 00-ff] 
 +[    1.708310] mt7621-pci 1e140000.pcie:      MEM 0x0060000000..0x006fffffff -> 0x0000000000 
 +[    1.724609] mt7621-pci 1e140000.pcie:       IO 0x001e160000..0x001e16ffff -> 0x0000000000 
 +[    1.741005] mt7621-pci-phy 1e149000.pcie-phy: PHY for 0xbe149000 (dual port = 1) 
 +[    1.756080] mt7621-pci-phy 1e14a000.pcie-phy: PHY for 0xbe14a000 (dual port = 0) 
 +[    1.771056] mt7621-pci 1e140000.pcie: failed to parse bus ranges property: -22 
 +[    1.885676] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz 
 +[    1.896793] mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz 
 +[    2.008087] mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK) 
 +[    2.021953] mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK) 
 +[    2.035828] mt7621-pci 1e140000.pcie: PCIE0 enabled 
 +[    2.045545] mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002 
 +[    2.064237] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00 
 +[    2.076912] pci_bus 0000:00: root bus resource [io  0x1e160000-0x1e16ffff] 
 +[    2.090605] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] 
 +[    2.104311] pci_bus 0000:00: root bus resource [bus 00-ff] 
 +[    2.115243] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff]) 
 +[    2.135558] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400 
 +[    2.147535] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x7fffffff] 
 +[    2.160029] pci 0000:00:00.0: reg 0x14: [mem 0x60200000-0x6020ffff] 
 +[    2.172588] pci 0000:00:00.0: supports D1 
 +[    2.180556] pci 0000:00:00.0: PME# supported from D0 D1 D3hot 
 +[    2.193637] pci 0000:01:00.0: [14c3:7615] type 00 class 0x000280 
 +[    2.205659] pci 0000:01:00.0: reg 0x10: initial BAR value 0x00000000 invalid 
 +[    2.219704] pci 0000:01:00.0: reg 0x10: [mem size 0x00100000 64bit] 
 +[    2.232378] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5.0 GT/s PCIe x1 link) 
 +[    2.263333] pci 0000:00:00.0: PCI bridge to [bus 01-ff] 
 +[    2.273774] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff] 
 +[    2.285909] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff] 
 +[    2.299438] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref] 
 +[    2.313832] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 
 +[    2.327044] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000] 
 +[    2.340217] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000] 
 +[    2.354100] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff] 
 +[    2.367620] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref] 
 +[    2.382010] pci 0000:00:00.0: BAR 1: assigned [mem 0x60200000-0x6020ffff] 
 +[    2.395544] pci 0000:00:00.0: BAR 7: assigned [io  0x1e160000-0x1e160fff] 
 +[    2.409069] pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x600fffff 64bit] 
 +[    2.423645] pci 0000:00:00.0: PCI bridge to [bus 01] 
 +[    2.433537] pci 0000:00:00.0:   bridge window [io  0x1e160000-0x1e160fff] 
 +[    2.447053] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff] 
 +[    2.460572] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref] 
 +[    2.483113] VFS: Mounted root (squashfs filesystem) readonly on device 31:6. 
 +[    2.501585] Freeing unused kernel memory: 1292K 
 +[    2.510618] This architecture does not have kernel memory protection. 
 +[    2.523474] Run /sbin/init as init process 
 +[    2.532065] mt7530 mdio-bus:1f: Link is Up - 1Gbps/Full - flow control rx/tx 
 +[    3.091762] init: Console is alive 
 +[    3.098900] init: - watchdog - 
 +[    3.926495] kmodloader: loading kernel modules from /etc/modules-boot.d/
 +[    4.057736] usbcore: registered new interface driver usbfs 
 +[    4.068905] usbcore: registered new interface driver hub 
 +[    4.079652] usbcore: registered new device driver usb 
 +[    4.094916] uhci_hcd: USB Universal Host Controller Interface driver 
 +[    4.115431] xhci-mtk 1e1c0000.xhci: supply vbus not found, using dummy regulator 
 +[    4.130503] xhci-mtk 1e1c0000.xhci: supply vusb33 not found, using dummy regulator 
 +[    4.145861] xhci-mtk 1e1c0000.xhci: xHCI Host Controller 
 +[    4.156504] xhci-mtk 1e1c0000.xhci: new USB bus registered, assigned bus number 1 
 +[    4.181382] xhci-mtk 1e1c0000.xhci: hcc params 0x01401198 hci version 0x96 quirks 0x0000000000290010 
 +[    4.199680] xhci-mtk 1e1c0000.xhci: irq 20, io mem 0x1e1c0000 
 +[    4.212492] hub 1-0:1.0: USB hub found 
 +[    4.220110] hub 1-0:1.0: 2 ports detected 
 +[    4.228828] xhci-mtk 1e1c0000.xhci: xHCI Host Controller 
 +[    4.239493] xhci-mtk 1e1c0000.xhci: new USB bus registered, assigned bus number 2 
 +[    4.254455] xhci-mtk 1e1c0000.xhci: Host supports USB 3.0 SuperSpeed 
 +[    4.267337] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. 
 +[    4.284367] hub 2-0:1.0: USB hub found 
 +[    4.292128] hub 2-0:1.0: 1 port detected 
 +[    4.307798] kmodloader: done loading kernel modules from /etc/modules-boot.d/
 +[    4.341696] init: - preinit - 
 +[    5.141616] random: jshn: uninitialized urandom read (4 bytes read) 
 +[    5.225812] random: jshn: uninitialized urandom read (4 bytes read) 
 +[    5.276679] random: jshn: uninitialized urandom read (4 bytes read) 
 +[    5.558866] mtk_soc_eth 1e100000.ethernet eth0: configuring for fixed/rgmii link mode 
 +[    5.575074] mtk_soc_eth 1e100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx 
 +[    5.581722] mt7530 mdio-bus:1f lan1: configuring for phy/gmii link mode 
 +[    5.605420] 8021q: adding VLAN 0 to HW filter on device lan1 
 +[    5.619351] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready 
 +Press the [f] key and hit [enter] to enter failsafe mode 
 +Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level 
 +[    9.844537] jffs2: notice: (594) jffs2_build_xattr_subsystem: complete building xattr subsystem, 17 of xdatum (7 unchecked, 6 orphan) and 33 of xref (16 dead, 3 orphan) found. 
 +[    9.877692] mount_root: switching to jffs2 overlay 
 +[    9.890793] overlayfs: upper fs does not support tmpfile. 
 +[    9.913579] urandom-seed: Seeding with /etc/urandom.seed 
 +[   10.035393] procd: - early - 
 +[   10.041547] procd: - watchdog - 
 +[   10.691412] procd: - watchdog - 
 +[   10.800394] procd: - ubus - 
 +[   10.939918] random: ubusd: uninitialized urandom read (4 bytes read) 
 +[   10.962090] random: ubusd: uninitialized urandom read (4 bytes read) 
 +[   10.975230] random: ubusd: uninitialized urandom read (4 bytes read) 
 +[   10.993925] procd: - init - 
 +Please press Enter to activate this console. 
 +[   11.302010] random: crng init done 
 +[   11.308805] random: 23 urandom warning(s) missed due to ratelimiting 
 +[   11.805305] kmodloader: loading kernel modules from /etc/modules.d/
 +[   11.959625] urngd: v1.0.2 started. 
 +[   12.114454] Loading modules backported from Linux version v5.15.58-0-g7d8048d4e064 
 +[   12.129581] Backport generated by backports.git v5.15.58-1-0-g42a95ce7 
 +[   12.357815] mt7621-pci 1e140000.pcie: bus=1 slot=0 irq=22 
 +[   12.368632] pci 0000:00:00.0: enabling device (0006 -> 0007) 
 +[   12.379910] mt7615e 0000:01:00.0: enabling device (0000 -> 0002) 
 +[   12.422109] mt7615e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20180518100604a 
 +[   12.422109] 
 +[   12.463889] PPP generic driver version 2.4.2 
 +[   12.474259] NET: Registered protocol family 24 
 +[   12.491054] kmodloader: done loading kernel modules from /etc/modules.d/
 +[   12.779876] mt7615e 0000:01:00.0: N9 Firmware Version: _reserved_, Build Time: 20200814163649 
 +[   12.893605] mt7615e 0000:01:00.0: CR4 Firmware Version: _reserved_, Build Time: 20190121161307 
 +[   21.120643] mtk_soc_eth 1e100000.ethernet eth0: Link is Down 
 +[   21.142190] mtk_soc_eth 1e100000.ethernet eth0: configuring for fixed/rgmii link mode 
 +[   21.158173] mtk_soc_eth 1e100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx 
 +[   21.161890] mt7530 mdio-bus:1f lan1: configuring for phy/gmii link mode 
 +[   21.188685] 8021q: adding VLAN 0 to HW filter on device lan1 
 +[   21.202988] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready 
 +[   21.216612] br-lan: port 1(lan1) entered blocking state 
 +[   21.227152] br-lan: port 1(lan1) entered disabled state 
 +[   21.238594] device lan1 entered promiscuous mode 
 +[   21.248127] device eth0 entered promiscuous mode 
 +[   21.281800] mt7530 mdio-bus:1f lan2: configuring for phy/gmii link mode 
 +[   21.295744] 8021q: adding VLAN 0 to HW filter on device lan2 
 +[   21.310521] br-lan: port 2(lan2) entered blocking state 
 +[   21.321272] br-lan: port 2(lan2) entered disabled state 
 +[   21.333088] device lan2 entered promiscuous mode 
 +[   21.356209] mt7530 mdio-bus:1f lan3: configuring for phy/gmii link mode 
 +[   21.370017] 8021q: adding VLAN 0 to HW filter on device lan3 
 +[   21.385072] br-lan: port 3(lan3) entered blocking state 
 +[   21.395668] br-lan: port 3(lan3) entered disabled state 
 +[   21.407601] device lan3 entered promiscuous mode 
 +[   21.429562] mt7530 mdio-bus:1f lan4: configuring for phy/gmii link mode 
 +[   21.443399] 8021q: adding VLAN 0 to HW filter on device lan4 
 +[   21.458194] br-lan: port 4(lan4) entered blocking state 
 +[   21.468678] br-lan: port 4(lan4) entered disabled state 
 +[   21.480536] device lan4 entered promiscuous mode 
 +[   21.508096] mtk_soc_eth 1e100000.ethernet wan: PHY [mdio-bus:04] driver [MediaTek MT7530 PHY] (irq=POLL) 
 +[   21.527082] mtk_soc_eth 1e100000.ethernet wan: configuring for phy/rgmii-rxid link mode</nowiki>
 </WRAP>\\ </WRAP>\\
  
 ===== Notes ===== ===== Notes =====
-//Space for additional notes, links to forum threads or other resources.// +Known problems:
- +
-  * ...+
  
 +  * WLAN0 defaults to 5G after a fresh installation, to enable 2.4G network, you need to config it manually in LUCI.
 +  * If you see jffs2 related warnings/errors after updating from the stock web interface, you need to do a reset in LUCI. The error will be gone after a cold reboot.
 ===== Tags ===== ===== Tags =====
 <WRAP BOX> <WRAP BOX>
  • Last modified: 2024/02/13 05:08
  • by rikka0w0