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| toh:d-link:dir-853_a1 [2024/02/12 23:39] – rotate summary tables jow | toh:d-link:dir-853_a1 [2024/02/13 05:05] – [Hardware mods] rikka0w0 | ||
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| Line 9: | Line 9: | ||
| {{media: | {{media: | ||
| - | ===== Supported Versions | + | |
| + | ===== Hardware Highlights | ||
| <!-- ToH: { | <!-- ToH: { | ||
| " | " | ||
| " | " | ||
| " | " | ||
| - | " | + | " |
| - | " | + | " |
| " | " | ||
| } --> | } --> | ||
| - | ===== Hardware Highlights | + | |
| + | ===== Supported Versions | ||
| <!-- ToH: { | <!-- ToH: { | ||
| " | " | ||
| " | " | ||
| " | " | ||
| - | " | + | " |
| - | " | + | " |
| " | " | ||
| } --> | } --> | ||
| - | |||
| - | ===== Installation ===== | ||
| <!-- ToH: { | <!-- ToH: { | ||
| " | " | ||
| Line 40: | Line 40: | ||
| } --> | } --> | ||
| - | - Open the case, and solder the 4-pin header near the WAN port. | ||
| - | - Connect it to a USB-UART TTL (3.3V) adapter, no need to connect VCC. | ||
| - | - Open a terminal emulator (e.g. screen / | ||
| - | - Setup a TFTP server on your PC that can serve xxx-ramips-mt7621-dlink_dir-853-a1-initramfs-kernel.bin. | ||
| - | - Connect any LAN port to your PC and set a static IPv4 address to 192.168.0.101 (netmask 255.255.255.0). | ||
| - | - Power on the device and keeps pressing 1 until you see the prompt. | ||
| - | - Use default IP addresses and enter the file name accordingly, | ||
| - | - Wait until it boots to OpenWrt, the default IP address is 192.168.1.1, | ||
| - | - So far, the OpenWrt runs in RAM and the flash contents are not touched. You can try OpenWrt without having to overwrite the stock firmware, a reboot clears all changes. | ||
| - | - Optionally, backup the stock firmware (the " | ||
| - | - To permantly install OpenWrt to the device , click on " | ||
| ==== OEM easy installation ==== | ==== OEM easy installation ==== | ||
| It is possible to install OpenWrt from the stock web interface without having to open the case of the router. [[docs: | It is possible to install OpenWrt from the stock web interface without having to open the case of the router. [[docs: | ||
| - | You would need the imgcrypt tool to encrypt a OpenWrt factory | + | **To walk around that and ease the installation of OpenWrt, first install this encrypted OpenWrt image (become dated), and then upgrade (using Luci Sysupgrade) to the latest OpenWrt: |
| + | |||
| + | https:// | ||
| + | |||
| + | The above image was generated by the imgcrypt | ||
| < | < | ||
| ./imgcrypt openwrt-ramips-mt7621-dlink_dir-853-a1-squashfs-factory.bin dir-853-a1-fac-enc.bin | ./imgcrypt openwrt-ramips-mt7621-dlink_dir-853-a1-squashfs-factory.bin dir-853-a1-fac-enc.bin | ||
| Line 61: | Line 54: | ||
| The imgcrypt tool is only available in source code at https:// | The imgcrypt tool is only available in source code at https:// | ||
| + | |||
| You need to compile it on a 32-bit Linux or add 32-bit support to your AMD64 Linux distro. | You need to compile it on a 32-bit Linux or add 32-bit support to your AMD64 Linux distro. | ||
| + | |||
| See: | See: | ||
| https:// | https:// | ||
| + | https:// | ||
| + | |||
| + | ===== Basic configuration ===== | ||
| + | -> [[docs: | ||
| + | |||
| + | Known problems: | ||
| + | |||
| + | * WLAN0 defaults to 5G after a fresh installation, | ||
| + | * If you see jffs2 related warnings/ | ||
| + | |||
| + | |||
| + | ==== OEM installation and Debricking using the serial TFTP method ==== | ||
| + | |||
| + | -> [[docs: | ||
| + | |||
| + | -> [[docs: | ||
| + | |||
| + | __Opening the case of the router may avoid its warranty. You may only consider this approach if you familiar with soldering. Otherwise, please proceed to **OEM easy installation**.__ | ||
| + | |||
| + | In this method, we first load an OpenWrt image into the RAM from the stock U-boot serial interface, then we install OpenWrt permanently to the flash. | ||
| + | |||
| + | - Open the case, and solder the 4-pin header near the WAN port. | ||
| + | - Connect it to a USB-UART TTL (3.3V) adapter, no need to connect VCC. | ||
| + | - Open a terminal emulator (e.g. '' | ||
| + | - Setup a TFTP server on your PC that can serve '' | ||
| + | - Connect any LAN port to your PC and set a static IPv4 address to '' | ||
| + | - Power on the device and keeps pressing 1 until you see the prompt. | ||
| + | - Use default IP addresses and enter the file name accordingly, | ||
| + | - Wait until it boots to OpenWrt, the default IP address is '' | ||
| + | - **So far, the OpenWrt runs in RAM and the flash contents are not touched.** You can try OpenWrt without having to overwrite the stock firmware, a reboot clears all changes. | ||
| + | - Optionally, backup the stock firmware (the " | ||
| + | - To permantly install OpenWrt to the device , click on " | ||
| + | |||
| + | Note: | ||
| + | |||
| + | **You should never flash images named '' | ||
| ===== Flash Layout ===== | ===== Flash Layout ===== | ||
| Line 83: | Line 114: | ||
| 0x000000fb0000-0x000001000000 : " | 0x000000fb0000-0x000001000000 : " | ||
| </ | </ | ||
| + | |||
| OpenWrt: | OpenWrt: | ||
| Line 93: | Line 125: | ||
| 0x000000fb0000-0x000001000000 : " | 0x000000fb0000-0x000001000000 : " | ||
| </ | </ | ||
| - | W.I.P | ||
| - | ^ | ||
| - | ^ Layer0 | ||
| - | ^ Layer1 | ||
| - | ^ Layer2 | + | ^ |
| - | ^ <color magenta> | + | ^ Layer0 |
| - | ^ filesystem | + | ^ Layer1 |
| - | ^ Layer3 | + | | **Layer2** |
| - | ^ Size in KiB | | + | | **Layer3** |
| - | ^ Name | **//u-boot//** | **// | + | | <color magenta>Mount Point</ |
| - | ^ <color magenta>mountpoint</ | + | | ::: | |
| - | ^ filesystem | + | |
| - | |||
| - | ==== OEM installation using the TFTP method ==== | ||
| - | |||
| - | -> [[docs: | ||
| - | |||
| - | === Specific values needed for tftp === | ||
| - | |||
| - | <WRAP BOX> | ||
| - | |||
| - | FIXME Enter values for " | ||
| - | |||
| - | ^ Bootloader tftp server IPv4 address | ||
| - | ^ Bootloader MAC address (special) | ||
| - | ^ Firmware tftp image | [[: | ||
| - | ^ TFTP transfer window | ||
| - | ^ TFTP window start | approximately FILL-IN seconds after power on | | ||
| - | ^ TFTP client required IP address | ||
| - | |||
| - | </ | ||
| ===== Upgrading OpenWrt ===== | ===== Upgrading OpenWrt ===== | ||
| -> [[docs: | -> [[docs: | ||
| - | <WRAP BOX> | + | Both LuCI web upgrade |
| - | + | ||
| - | FIXME These are generic instructions. Update with your router' | + | |
| - | + | ||
| - | ==== LuCI Web Upgrade Process ==== | + | |
| - | + | ||
| - | * Browse to ''< | + | |
| - | * Upload image file for sysupgrade to LuCI | + | |
| - | * Wait for reboot | + | |
| - | + | ||
| - | ==== Terminal Upgrade Process ==== | + | |
| - | + | ||
| - | If you don't have a GUI (LuCI) available, you can alternatively | + | |
| - | There are two command line methods for upgrading: | + | |
| - | + | ||
| - | * '' | + | |
| - | * '' | + | |
| - | + | ||
| - | Note: It is important that you put the firmware image into the ramdisk (/tmp) before you start flashing. | + | |
| - | + | ||
| - | === sysupgrade === | + | |
| - | + | ||
| - | * Login as root via SSH on 192.168.1.1, | + | |
| - | + | ||
| - | < | + | |
| - | cd /tmp | + | |
| - | wget http:// | + | |
| - | sysupgrade / | + | |
| - | </ | + | |
| - | + | ||
| - | === mtd === | + | |
| - | + | ||
| - | If '' | + | |
| - | + | ||
| - | * Login as root via SSH on 192.168.1.1, | + | |
| - | + | ||
| - | < | + | |
| - | cd /tmp | + | |
| - | wget http:// | + | |
| - | mtd write / | + | |
| - | </ | + | |
| - | + | ||
| - | </ | + | |
| - | + | ||
| - | ===== Debricking ===== | + | |
| - | -> [[docs: | + | |
| ===== Failsafe mode ===== | ===== Failsafe mode ===== | ||
| -> [[docs: | -> [[docs: | ||
| - | ===== Basic configuration ===== | ||
| - | -> [[docs: | ||
| - | Set up your Internet connection, configure wireless, configure USB port, etc. | ||
| - | ===== Specific Configuration ===== | ||
| - | <WRAP BOX> | + | ===== Hardware ===== |
| - | FIXME Please fill in real values for this device, then remove | + | ==== MAC addresses on OEM firmware ==== |
| + | ^ Interface Name ^ Location on the flash ^ Note ^ | ||
| + | | lan (eth2) | ||
| + | | wan (eth3) | ||
| + | | 2.4g (rax0) | ||
| + | | 5g (ra0) | not on flash | lan + 2 | | ||
| - | ==== Network interfaces | + | ==== Info ==== |
| - | The default network configuration is: | + | |
| - | ^ Interface Name ^ Description | + | |
| - | | br-lan | + | |
| - | | vlan0 (eth0.0) | + | |
| - | | vlan1 (eth0.1) | + | |
| - | | wl0 | EXAMPLE WiFi | EXAMPLE Disabled | + | |
| - | </ | + | * LEDs: Power Blue+Orange, |
| + | * Buttons: Reset,WPS, Wifi | ||
| - | ==== Switch Ports (for VLANs) ==== | ||
| - | <WRAP BOX> | ||
| - | FIXME Please fill in real values for this device, then remove the EXAMPLEs | ||
| - | |||
| - | Numbers 0-3 are Ports 1-4 as labeled on the unit, number 4 is the Internet (WAN) on the unit, 5 is the internal connection to the router itself. Don't be fooled: Port 1 on the unit is number 3 when configuring VLANs. vlan0 = eth0.0, vlan1 = eth0.1 and so on. | ||
| - | ^ Port ^ Switch port ^ | ||
| - | | Internet (WAN) | EXAMPLE 4 | | ||
| - | | LAN 1 | EXAMPLE 3 | | ||
| - | | LAN 2 | EXAMPLE 2 | | ||
| - | | LAN 3 | EXAMPLE 1 | | ||
| - | | LAN 4 | EXAMPLE 0 | | ||
| - | |||
| - | </ | ||
| - | |||
| - | ==== Buttons ==== | ||
| - | -> [[docs: | ||
| - | Here, we merely name the buttons, so we can use them in the above Howto. | ||
| - | |||
| - | <WRAP BOX> | ||
| - | FIXME Please fill in real values for this device, then remove the EXAMPLEs | ||
| - | |||
| - | The D-Link DIR-853 has the following buttons: | ||
| - | |||
| - | ^ BUTTON | ||
| - | | EXAMPLE Reset | reset | | ||
| - | | EXAMPLE Secure Easy Setup | | ||
| - | | EXAMPLE No buttons at all. | ||
| - | |||
| - | </ | ||
| - | |||
| - | ===== Hardware ===== | ||
| - | ==== Info ==== | ||
| <WRAP BOX> | <WRAP BOX> | ||
| FIXME | FIXME | ||
| Line 248: | Line 175: | ||
| ---- | ---- | ||
| - | ==== Photos ==== | ||
| - | /* =====>>>>> | ||
| - | /* When uploading photos, **name them** intelligently. Nobody knows what 20100930_000602.jpg is! */ | ||
| - | /* e.g. {{: | ||
| - | /* Thanks, your wiki administration - Oct. 2015 */ | ||
| - | // | + | ==== Opening |
| - | **Insert photo of front of the casing** | + | |
| - | // | + | Remove four screws on the bottom |
| - | **Insert photo of back of the casing** | + | |
| - | + | ||
| - | //Backside label:// | + | |
| - | **Insert photo of backside label** | + | |
| - | + | ||
| - | ==== Opening | + | |
| **Note:** This will void your warranty! | **Note:** This will void your warranty! | ||
| - | |||
| - | <WRAP BOX> | ||
| - | FIXME //Describe what needs to be done to open the device, e.g. remove rubber feet, adhesive labels, screws, ...// | ||
| - | * To remove the cover and open the device, do a/b/c | ||
| - | </ | ||
| //Main PCB://\\ | //Main PCB://\\ | ||
| - | **Insert photo of PCB** | + | {{media: |
| ==== Serial ==== | ==== Serial ==== | ||
| -> [[docs: | -> [[docs: | ||
| - | How to connect to the Serial Port of this specific device:\\ | + | The serial |
| - | **Insert photo of PCB with markings for serial | + | |
| - | <WRAP BOX> | + | ^ Serial connection parameters\\ for D-Link DIR-853 A1 | 57600, 8N1, 3.3V | |
| - | FIXME //Replace EXAMPLE by real values.// | + | |
| - | </ | + | |
| - | ^ Serial connection parameters\\ for D-Link DIR-853 A1 | EXAMPLE 115200, 8N1, 3.3V | | + | There is no need to connect Vcc to an external |
| - | ==== JTAG ==== | + | {{media:dlink:dir-853_a1:serial.png}} |
| - | -> [[docs:techref:hardware:port.jtag]] general information about the JTAG port, JTAG cable, etc. | + | |
| - | + | ||
| - | How to connect to the JTAG Port of this specific device:\\ | + | |
| - | **Insert photo of PCB with markings for JTAG port** | + | |
| ===== Bootloader mods ===== | ===== Bootloader mods ===== | ||
| Line 298: | Line 200: | ||
| ===== Hardware mods ===== | ===== Hardware mods ===== | ||
| - | None so far. | + | **Not verified!** |
| + | |||
| + | There is an unpopulated USB 2.0 port on the PCB. To use it, you need to short circuit R31, LB15, R35, R38, and R37 on the PCB: | ||
| + | |||
| + | {{media: | ||
| + | |||
| + | The pin out of the USB socket (from the top to bottom) is: | ||
| + | - Vcc, 5V | ||
| + | - D- | ||
| + | - D+ | ||
| + | - GND | ||
| + | |||
| + | This port should work on the official OpenWrt firmware, as '' | ||
| Line 309: | Line 223: | ||
| ==== OpenWrt bootlog ==== | ==== OpenWrt bootlog ==== | ||
| <WRAP bootlog> | <WRAP bootlog> | ||
| - | < | + | < |
| + | MT7621 | ||
| + | CPU=500000000 HZ BUS=166666666 HZ | ||
| + | ================================================================== | ||
| + | Change MPLL source from XTAL to CR... | ||
| + | do MEMPLL setting.. | ||
| + | MEMPLL Config : 0x11100000 | ||
| + | 3PLL mode + External loopback | ||
| + | === XTAL-40Mhz === DDR-1200Mhz === | ||
| + | PLL4 FB_DL: 0x6, 1/0 = 580/444 19000000 | ||
| + | PLL2 FB_DL: 0x10, 1/0 = 563/461 41000000 | ||
| + | PLL3 FB_DL: 0x11, 1/0 = 587/437 45000000 | ||
| + | do DDR setting..[01F40000] | ||
| + | Apply DDR3 Setting...(use customer AC) | ||
| + | 0 8 | ||
| + | -------------------------------------------------------------------------------- | ||
| + | 0000: | ||
| + | 0001: | ||
| + | 0002: | ||
| + | 0003: | ||
| + | 0004: | ||
| + | 0005: | ||
| + | 0006: | ||
| + | 0007: | ||
| + | 0008: | ||
| + | 0009: | ||
| + | 000A: | ||
| + | 000B: | ||
| + | 000C: | ||
| + | 000D: | ||
| + | 000E: | ||
| + | 000F: | ||
| + | 0010: | ||
| + | 0011: | ||
| + | 0012: | ||
| + | 0013: | ||
| + | 0014: | ||
| + | 0015: | ||
| + | 0016: | ||
| + | 0017: | ||
| + | 0018: | ||
| + | 0019: | ||
| + | 001A: | ||
| + | 001B: | ||
| + | 001C: | ||
| + | 001D: | ||
| + | 001E: | ||
| + | 001F: | ||
| + | rank 0 coarse = 15 | ||
| + | rank 0 fine = 72 | ||
| + | B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 | ||
| + | opt_dle value:9 | ||
| + | DRAMC_R0DELDLY[018]=00001F20 | ||
| + | ================================================================== | ||
| + | RX DQS perbit delay software calibration | ||
| + | ================================================================== | ||
| + | 1.0-15 bit dq delay value | ||
| + | ================================================================== | ||
| + | bit| | ||
| + | -------------------------------------- | ||
| + | 0 | 10 10 10 11 8 9 10 7 7 8 | ||
| + | 10 | 9 9 9 10 9 10 | ||
| + | -------------------------------------- | ||
| + | |||
| + | ================================================================== | ||
| + | 2.dqs window | ||
| + | x=pass dqs delay value (min~max)center | ||
| + | y=0-7bit DQ of every group | ||
| + | input delay:DQS0 =32 DQS1 = 31 | ||
| + | ================================================================== | ||
| + | bit | ||
| + | 0 (1~62)31 | ||
| + | 1 (1~64)32 | ||
| + | 2 (1~60)30 | ||
| + | 3 (1~62)31 | ||
| + | 4 (1~60)30 | ||
| + | 5 (1~64)32 | ||
| + | 6 (1~62)31 | ||
| + | 7 (1~64)32 | ||
| + | ================================================================== | ||
| + | 3.dq delay value last | ||
| + | ================================================================== | ||
| + | bit| 0 1 2 3 4 5 6 7 8 9 | ||
| + | -------------------------------------- | ||
| + | 0 | 11 10 12 12 10 9 11 7 9 9 | ||
| + | 10 | 9 12 10 11 9 10 | ||
| + | ================================================================== | ||
| + | ================================================================== | ||
| + | | ||
| + | ================================================================== | ||
| + | DQS loop = 15, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[0]=15, | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[1]=15, | ||
| + | DQ loop=15, cmp_err_1 = ffff00a0 | ||
| + | dqs_perbyte_dly.last_dqdly_pass[1]=15, | ||
| + | DQ loop=14, cmp_err_1 = ffff0080 | ||
| + | DQ loop=13, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqdly_pass[0]=13, | ||
| + | byte:0, (DQS, | ||
| + | byte:1, (DQS, | ||
| + | 20, | ||
| + | [EMI] DRAMC calibration passed | ||
| + | |||
| + | =================================================================== | ||
| + | MT7621 | ||
| + | CPU=500000000 HZ BUS=166666666 HZ | ||
| + | =================================================================== | ||
| + | |||
| + | |||
| + | U-Boot 1.1.3 (Jun 27 2019 - 20:25:37) | ||
| + | |||
| + | Board: Ralink APSoC DRAM: 128 MB | ||
| + | relocate_code Pointer at: 87fa8000 | ||
| + | |||
| + | Config XHCI 40M PLL | ||
| + | ****************************** | ||
| + | Software System Reset Occurred | ||
| + | ****************************** | ||
| + | flash manufacture id: c8, device id 40 18 | ||
| + | find flash: GD25Q128C | ||
| + | ============================================ | ||
| + | Ralink UBoot Version: 5.0.0.0 | ||
| + | -------------------------------------------- | ||
| + | ASIC MT7621A DualCore (MAC to MT7530 Mode) | ||
| + | DRAM_CONF_FROM: | ||
| + | DRAM_TYPE: DDR3 | ||
| + | DRAM bus: 16 bit | ||
| + | Xtal Mode=3 OCP Ratio=1/3 | ||
| + | Flash component: SPI Flash | ||
| + | Date:Jun 27 2019 Time: | ||
| + | ============================================ | ||
| + | icache: sets:256, ways:4, linesz:32 , | ||
| + | dcache: sets:256, ways:4, linesz:32 , | ||
| + | |||
| + | ##### The CPU freq = 880 MHZ #### | ||
| + | | ||
| + | # | ||
| + | set LAN/WAN LLLLW | ||
| + | ######## | ||
| + | |||
| + | Please choose the operation: | ||
| + | 1: Load system code to SDRAM via TFTP. | ||
| + | 2: Load system code then write to Flash via TFTP. | ||
| + | 3: Boot system code via Flash (default). | ||
| + | 4: Entr boot command line interface. | ||
| + | 6: System Enter UBoot to Update Img or Bin. | ||
| + | 7: Load Boot Loader code then write to Flash via Serial. | ||
| + | 9: Load Boot Loader code then write to Flash via TFTP. | ||
| + | default: 3 0 | ||
| + | |||
| + | 3: System Boot system code via Flash. | ||
| + | ## Booting image at bc060000 ... | ||
| + | Image Name: MIPS OpenWrt Linux-5.10.146 | ||
| + | Image Type: MIPS Linux Kernel Image (lzma compressed) | ||
| + | Data Size: 2708134 Bytes = 2.6 MB | ||
| + | Load Address: 80001000 | ||
| + | Entry Point: | ||
| + | | ||
| + | | ||
| + | No initrd | ||
| + | ## Transferring control to Linux (at address 80001000) ... | ||
| + | ## Giving linux memsize in MB, 128 | ||
| + | |||
| + | Starting kernel ... | ||
| + | |||
| + | [ 0.000000] Linux version 5.10.146 (builder@buildhost) (mipsel-openwrt-linux-musl-gcc (OpenWrt GCC 11.2.0 r19803-9a599fee93) 11.2.0, GNU ld (GNU Binutils) 2.37) #0 SMP Fri Oct 14 22:44:41 2022 | ||
| + | [ 0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3 | ||
| + | [ 0.000000] printk: bootconsole [early0] enabled | ||
| + | [ 0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.000000] MIPS: machine is D-Link DIR-853 A1 | ||
| + | [ 0.000000] Initrd not found or empty - disabling initrd | ||
| + | [ 0.000000] VPE topology {2,2} total 4 | ||
| + | [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.000000] Zone ranges: | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] Movable zone start for each node | ||
| + | [ 0.000000] Early memory node ranges | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff] | ||
| + | [ 0.000000] percpu: Embedded 15 pages/cpu s30256 r8192 d22992 u61440 | ||
| + | [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 32480 | ||
| + | [ 0.000000] Kernel command line: console=ttyS0, | ||
| + | [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear) | ||
| + | [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear) | ||
| + | [ 0.000000] Writing ErrCtl register=00016080 | ||
| + | [ 0.000000] Readback ErrCtl register=00016080 | ||
| + | [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off | ||
| + | [ 0.000000] Memory: 119472K/ | ||
| + | [ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, | ||
| + | [ 0.000000] rcu: Hierarchical RCU implementation. | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. | ||
| + | [ 0.000000] NR_IRQS: 256 | ||
| + | [ 0.000000] CPU Clock: 880MHz | ||
| + | [ 0.000000] clocksource: | ||
| + | [ 0.000013] sched_clock: | ||
| + | [ 0.015853] clocksource: | ||
| + | [ 0.033805] Calibrating delay loop... 586.13 BogoMIPS (lpj=2930688) | ||
| + | [ 0.106122] pid_max: default: 32768 minimum: 301 | ||
| + | [ 0.115430] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) | ||
| + | [ 0.129834] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) | ||
| + | [ 0.148078] rcu: Hierarchical SRCU implementation. | ||
| + | [ 0.157881] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build | ||
| + | [ 0.173444] smp: Bringing up secondary CPUs ... | ||
| + | [ 0.183187] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.183197] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.183209] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.183284] CPU1 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.243287] Synchronize counters for CPU 1: done. | ||
| + | [ 0.305407] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.305417] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.305425] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.305473] CPU2 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.364384] Synchronize counters for CPU 2: done. | ||
| + | [ 0.424710] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.424719] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.424728] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.424781] CPU3 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.483959] Synchronize counters for CPU 3: done. | ||
| + | [ 0.543570] smp: Brought up 1 node, 4 CPUs | ||
| + | [ 0.555778] clocksource: | ||
| + | [ 0.575280] futex hash table entries: 1024 (order: 3, 32768 bytes, linear) | ||
| + | [ 0.589099] pinctrl core: initialized pinctrl subsystem | ||
| + | [ 0.601798] NET: Registered protocol family 16 | ||
| + | [ 0.611696] thermal_sys: | ||
| + | [ 0.613145] cpuidle: using governor teo | ||
| + | [ 0.671207] clocksource: | ||
| + | [ 0.682995] NET: Registered protocol family 2 | ||
| + | [ 0.691984] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear) | ||
| + | [ 0.707203] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear) | ||
| + | [ 0.723831] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear) | ||
| + | [ 0.739004] TCP bind hash table entries: 1024 (order: 1, 8192 bytes, linear) | ||
| + | [ 0.752943] TCP: Hash tables configured (established 1024 bind 1024) | ||
| + | [ 0.765714] UDP hash table entries: 256 (order: 1, 8192 bytes, linear) | ||
| + | [ 0.778604] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear) | ||
| + | [ 0.792725] NET: Registered protocol family 1 | ||
| + | [ 0.801309] PCI: CLS 0 bytes, default 32 | ||
| + | [ 0.811464] workingset: timestamp_bits=14 max_order=15 bucket_order=1 | ||
| + | [ 0.828391] squashfs: version 4.0 (2009/ | ||
| + | [ 0.839898] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc. | ||
| + | [ 0.860175] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251) | ||
| + | [ 0.876552] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.887905] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.899236] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.911221] Serial: 8250/16550 driver, 16 ports, IRQ sharing enabled | ||
| + | [ 0.928100] printk: console [ttyS0] disabled | ||
| + | [ 0.936579] 1e000c00.uartlite: | ||
| + | [ 0.954502] printk: console [ttyS0] enabled | ||
| + | [ 0.954502] printk: console [ttyS0] enabled | ||
| + | [ 0.971027] printk: bootconsole [early0] disabled | ||
| + | [ 0.971027] printk: bootconsole [early0] disabled | ||
| + | [ 0.992973] spi-mt7621 1e000b00.spi: | ||
| + | [ 1.005150] spi-nor spi0.0: gd25q128 (16384 Kbytes) | ||
| + | [ 1.014989] 6 fixed-partitions partitions found on MTD device spi0.0 | ||
| + | [ 1.027693] OF: Bad cell count for / | ||
| + | [ 1.042271] OF: Bad cell count for / | ||
| + | [ 1.057656] OF: Bad cell count for / | ||
| + | [ 1.072275] OF: Bad cell count for / | ||
| + | [ 1.087061] Creating 6 MTD partitions on " | ||
| + | [ 1.096617] 0x000000000000-0x000000030000 : " | ||
| + | [ 1.107509] 0x000000030000-0x000000040000 : " | ||
| + | [ 1.119251] 0x000000040000-0x000000050000 : " | ||
| + | [ 1.130404] 0x000000050000-0x000000060000 : " | ||
| + | [ 1.142841] 0x000000060000-0x000000fb0000 : " | ||
| + | [ 1.154222] 2 uimage-fw partitions found on MTD device firmware | ||
| + | [ 1.166043] Creating 2 MTD partitions on " | ||
| + | [ 1.175933] 0x000000000000-0x000000295346 : " | ||
| + | [ 1.185842] mtd: partition " | ||
| + | [ 1.203361] 0x000000295346-0x000000f50000 : " | ||
| + | [ 1.213272] mtd: partition " | ||
| + | [ 1.232457] mtd: device 6 (rootfs) set to be root filesystem | ||
| + | [ 1.243867] 1 squashfs-split partitions found on MTD device rootfs | ||
| + | [ 1.256181] 0x0000006c0000-0x000000f50000 : " | ||
| + | [ 1.267905] 0x000000fb0000-0x000001000000 : " | ||
| + | [ 1.322403] mt7530 mdio-bus: | ||
| + | [ 1.339352] mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 21 | ||
| + | [ 1.357067] mtk_soc_eth 1e100000.ethernet wan: mediatek frame engine at 0xbe100000, irq 21 | ||
| + | [ 1.374602] i2c /dev entries driver | ||
| + | [ 1.384253] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.397659] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.415203] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.431507] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.447886] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.460516] NET: Registered protocol family 10 | ||
| + | [ 1.471303] Segment Routing with IPv6 | ||
| + | [ 1.478696] NET: Registered protocol family 17 | ||
| + | [ 1.487665] bridge: filtering via arp/ | ||
| + | [ 1.513867] 8021q: 802.1Q VLAN Support v1.8 | ||
| + | [ 1.525571] mt7530 mdio-bus: | ||
| + | [ 1.554143] mt7530 mdio-bus:1f lan4 (uninitialized): | ||
| + | [ 1.576200] mt7530 mdio-bus:1f lan3 (uninitialized): | ||
| + | [ 1.598237] mt7530 mdio-bus:1f lan2 (uninitialized): | ||
| + | [ 1.620329] mt7530 mdio-bus:1f lan1 (uninitialized): | ||
| + | [ 1.643277] mt7530 mdio-bus: | ||
| + | [ 1.660099] DSA: tree 0 setup | ||
| + | [ 1.666369] rt2880-pinmux pinctrl: pcie is already enabled | ||
| + | [ 1.677406] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.690785] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.708310] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.724609] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.741005] mt7621-pci-phy 1e149000.pcie-phy: | ||
| + | [ 1.756080] mt7621-pci-phy 1e14a000.pcie-phy: | ||
| + | [ 1.771056] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.885676] mt7621-pci-phy 1e149000.pcie-phy: | ||
| + | [ 1.896793] mt7621-pci-phy 1e14a000.pcie-phy: | ||
| + | [ 2.008087] mt7621-pci 1e140000.pcie: | ||
| + | [ 2.021953] mt7621-pci 1e140000.pcie: | ||
| + | [ 2.035828] mt7621-pci 1e140000.pcie: | ||
| + | [ 2.045545] mt7621-pci 1e140000.pcie: | ||
| + | [ 2.064237] mt7621-pci 1e140000.pcie: | ||
| + | [ 2.076912] pci_bus 0000:00: root bus resource [io 0x1e160000-0x1e16ffff] | ||
| + | [ 2.090605] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] | ||
| + | [ 2.104311] pci_bus 0000:00: root bus resource [bus 00-ff] | ||
| + | [ 2.115243] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff]) | ||
| + | [ 2.135558] pci 0000: | ||
| + | [ 2.147535] pci 0000: | ||
| + | [ 2.160029] pci 0000: | ||
| + | [ 2.172588] pci 0000: | ||
| + | [ 2.180556] pci 0000: | ||
| + | [ 2.193637] pci 0000: | ||
| + | [ 2.205659] pci 0000: | ||
| + | [ 2.219704] pci 0000: | ||
| + | [ 2.232378] pci 0000: | ||
| + | [ 2.263333] pci 0000: | ||
| + | [ 2.273774] pci 0000: | ||
| + | [ 2.285909] pci 0000: | ||
| + | [ 2.299438] pci 0000: | ||
| + | [ 2.313832] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 | ||
| + | [ 2.327044] pci 0000: | ||
| + | [ 2.340217] pci 0000: | ||
| + | [ 2.354100] pci 0000: | ||
| + | [ 2.367620] pci 0000: | ||
| + | [ 2.382010] pci 0000: | ||
| + | [ 2.395544] pci 0000: | ||
| + | [ 2.409069] pci 0000: | ||
| + | [ 2.423645] pci 0000: | ||
| + | [ 2.433537] pci 0000: | ||
| + | [ 2.447053] pci 0000: | ||
| + | [ 2.460572] pci 0000: | ||
| + | [ 2.483113] VFS: Mounted root (squashfs filesystem) readonly on device 31:6. | ||
| + | [ 2.501585] Freeing unused kernel memory: 1292K | ||
| + | [ 2.510618] This architecture does not have kernel memory protection. | ||
| + | [ 2.523474] Run /sbin/init as init process | ||
| + | [ 2.532065] mt7530 mdio-bus: | ||
| + | [ 3.091762] init: Console is alive | ||
| + | [ 3.098900] init: - watchdog - | ||
| + | [ 3.926495] kmodloader: loading kernel modules from / | ||
| + | [ 4.057736] usbcore: registered new interface driver usbfs | ||
| + | [ 4.068905] usbcore: registered new interface driver hub | ||
| + | [ 4.079652] usbcore: registered new device driver usb | ||
| + | [ 4.094916] uhci_hcd: USB Universal Host Controller Interface driver | ||
| + | [ 4.115431] xhci-mtk 1e1c0000.xhci: | ||
| + | [ 4.130503] xhci-mtk 1e1c0000.xhci: | ||
| + | [ 4.145861] xhci-mtk 1e1c0000.xhci: | ||
| + | [ 4.156504] xhci-mtk 1e1c0000.xhci: | ||
| + | [ 4.181382] xhci-mtk 1e1c0000.xhci: | ||
| + | [ 4.199680] xhci-mtk 1e1c0000.xhci: | ||
| + | [ 4.212492] hub 1-0:1.0: USB hub found | ||
| + | [ 4.220110] hub 1-0:1.0: 2 ports detected | ||
| + | [ 4.228828] xhci-mtk 1e1c0000.xhci: | ||
| + | [ 4.239493] xhci-mtk 1e1c0000.xhci: | ||
| + | [ 4.254455] xhci-mtk 1e1c0000.xhci: | ||
| + | [ 4.267337] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. | ||
| + | [ 4.284367] hub 2-0:1.0: USB hub found | ||
| + | [ 4.292128] hub 2-0:1.0: 1 port detected | ||
| + | [ 4.307798] kmodloader: done loading kernel modules from / | ||
| + | [ 4.341696] init: - preinit - | ||
| + | [ 5.141616] random: jshn: uninitialized urandom read (4 bytes read) | ||
| + | [ 5.225812] random: jshn: uninitialized urandom read (4 bytes read) | ||
| + | [ 5.276679] random: jshn: uninitialized urandom read (4 bytes read) | ||
| + | [ 5.558866] mtk_soc_eth 1e100000.ethernet eth0: configuring for fixed/rgmii link mode | ||
| + | [ 5.575074] mtk_soc_eth 1e100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx | ||
| + | [ 5.581722] mt7530 mdio-bus:1f lan1: configuring for phy/gmii link mode | ||
| + | [ 5.605420] 8021q: adding VLAN 0 to HW filter on device lan1 | ||
| + | [ 5.619351] IPv6: ADDRCONF(NETDEV_CHANGE): | ||
| + | Press the [f] key and hit [enter] to enter failsafe mode | ||
| + | Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level | ||
| + | [ 9.844537] jffs2: notice: (594) jffs2_build_xattr_subsystem: | ||
| + | [ 9.877692] mount_root: switching to jffs2 overlay | ||
| + | [ 9.890793] overlayfs: upper fs does not support tmpfile. | ||
| + | [ 9.913579] urandom-seed: | ||
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| + | Please press Enter to activate this console. | ||
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| </ | </ | ||
| ===== Notes ===== | ===== Notes ===== | ||
| - | //Space for additional notes, links to forum threads or other resources.// | + | Known problems: |
| - | + | ||
| - | * ... | + | |
| + | * WLAN0 defaults to 5G after a fresh installation, | ||
| + | * If you see jffs2 related warnings/ | ||
| ===== Tags ===== | ===== Tags ===== | ||
| <WRAP BOX> | <WRAP BOX> | ||