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inbox:toh:arcadyan:astoria:we420223-99 [2022/10/09 19:07] – WIP harminbox:toh:arcadyan:astoria:we420223-99 [2023/05/18 16:51] – [Flashing via the original web interface] Fix list harm
Line 1: Line 1:
 ====== Arcadyan WE420223-99 ====== ====== Arcadyan WE420223-99 ======
-{{page>meta:infobox:construction&noheader&nofooter&noeditbtn}} 
- 
-//Write a short, relevant description of the device. Include a technical overview, but avoid marketing buzzwords/useless stuff. Two to four sentences is about right. A picture is good, too. Edit the page to see how to add pictures.// 
- 
 The Arcadyan WE420223-99 is an access point distributed by KPN in the Netherlands under the name "Experia WiFi". It has two ethernet ports and simultaneous dual band with ac support. The Arcadyan WE420223-99 is an access point distributed by KPN in the Netherlands under the name "Experia WiFi". It has two ethernet ports and simultaneous dual band with ac support.
  
Line 11: Line 7:
 ===== OpenWrt support ===== ===== OpenWrt support =====
  
-Official support is pendingpatches are available:+There is no stable release yet that supports this devicethere are snapshot releases though. 
  
-  * Patchwork patch: https://patchwork.ozlabs.org/project/openwrt/list/?series=313820 
-  * GitHub fork: https://github.com/hberntsen/openwrt-experia-wifi 
   * OpenWrt forum thread: https://forum.openwrt.org/t/adding-openwrt-support-for-arcadyan-we420223-99-kpn-experia-wifi/132653   * OpenWrt forum thread: https://forum.openwrt.org/t/adding-openwrt-support-for-arcadyan-we420223-99-kpn-experia-wifi/132653
   * Tweakers forum thread: https://gathering.tweakers.net/forum/list_messages/1882915   * Tweakers forum thread: https://gathering.tweakers.net/forum/list_messages/1882915
Line 29: Line 23:
  
 ===== Installation ===== ===== Installation =====
-This device is not officially supported by OpenWRT so there are no official builds for this device. Build it yourselfuse the following settings in ''menuconfig'': +If you are running an old firmware version that is equipped with a firmware upload page, that is usable for upgrading to OpenWRT, see 'Flashing via the original web interfacebelow.
-<code> +
-Target System (MediaTek Ralink MIPS) +
-Subtarget (MT7621 based boards) +
-Target Profile (Arcadyan WE420223-99) +
-</code> +
-Or ask for a build in the forum thread.+
  
-Unfortunately, the official firmware's U-Boot is [[https://forum.openwrt.org/t/adding-openwrt-support-for-arcadyan-we420223-99-kpn-experia-wifi/132653/5?u=harm|password protected]]. Furthermore, the official firmware does not accept unsigned firmware versions. You might be able to [[https://7bits.nl/journal/posts/cve-2021-38703-kpn-experia-wifi-root-shell/|gain root]] on firmware 1.00.15 and flash from there. Unless another exploit is found, OpenWRT needs to be directly written to the flash chip. The upside of this is that you don't need to solder the serial port.+Otherwisewe need to directly write to the flash chip since the official firmware's U-Boot is [[https://forum.openwrt.org/t/adding-openwrt-support-for-arcadyan-we420223-99-kpn-experia-wifi/132653/5?u=harm|password protected]]. The upside of this is that you don't need to solder the serial port.
  
-==== Connecting the flash chip to a Raspberry Pi ==== +==== Flashing via the original web interface ====
-A Raspberry Pi can be used to program the flash chip in-circuit (thanks FPSUsername for discovering). Connect the chip directly to the Raspberry Pi's SPI pins. You can solder wires to the flash chip but using a [[https://a.aliexpress.com/_v4MHHw|clip]] is easier. Make sure to connect the RESET pin to VCC for stability.+
  
-On the Raspberry Pi, you can use a specially crafted overlay for accessing the chip: https://gist.github.com/hberntsen/f37f5047a61c2cfeeaa1e3d0c2f7f033 .+The original firmware requires signed firmware. The code to do so is on GitHub: https://github.com/hberntsen/we420223-99-sign . You can download a signed OpenWRT initramfs image here: https://mega.nz/file/FjlgQKqD#23bEq46EiVqxMhGuwucYYpN4sbw2q1nLgmtimLORvFA .
  
-Download this file and install it with ''sudo dtc -@ -I dts -O dtb -o /boot/overlays/we420223.dtbo  we420223-99_overlay.dts''.+  - Flash the signed image via the web interface. OpenWRT should boot and start a DHCP server. 
 +  - Go to http://192.168.1.1/ and flash a new sysupgrade.bin file 
 +  - Profit! You might still want to unlock the U-Boot password for recovery in the future (see below) 
 +==== Writing directly to the flash chip ==== 
 +=== Connecting the flash chip to a Raspberry Pi === 
 +A Raspberry Pi can be used to program the flash chip in-circuit (thanks FPSUsername for discovering). On the Raspberry Pi, install ''xxd libubootenv-tool mtd-utils'' using ''apt'' on Raspberry Pi OS. To access the flash chip we have a specially crafted overlay: https://gist.github.com/hberntsen/f37f5047a61c2cfeeaa1e3d0c2f7f033. Download this file and install it with ''sudo dtc -@ -I dts -O dtb -o /boot/overlays/we420223.dtbo  we420223-99_overlay.dts''.
 Enable it in ''/boot/config.txt'' by adding a new line containing ''dtoverlay=we420223''. Enable it in ''/boot/config.txt'' by adding a new line containing ''dtoverlay=we420223''.
 +
 +Connect the chip directly to the Raspberry Pi's SPI pins. Use the following connections:
 +
 +{{:media:arcadyan:we420223-99-flash.png?400|}}
 +
 +^ Flash Chip  ^ Raspberry Pi         ^
 +| VCC         | 3v3                  |
 +| RESET       | 3v3                  |
 +| /CS         | GPIO 8 (SPI0 CE0)    |
 +| DO          | GPIO 9 (SPI0 MISO)   |
 +| CLK         | GPIO11 (SPI0 SCLK)   |
 +| DI          | GPIO 10 (SPI0 MOSI)  |
 +| GND         | Ground               |
 +
 +You can solder wires to the flash chip but using a [[https://a.aliexpress.com/_v4MHHw|clip]] is easier. Make sure to connect the RESET pin to VCC for stability.
  
 After connecting the flash chip and rebooting, the ''/dev/mtd*'' devices should be available. Run ''sudo apt install xxd libubootenv-tool mtd-utils'' to install the required software for flashing. After connecting the flash chip and rebooting, the ''/dev/mtd*'' devices should be available. Run ''sudo apt install xxd libubootenv-tool mtd-utils'' to install the required software for flashing.
  
-==== Creating a backup ====+=== Creating a backup ===
 For recovery, creating a backup of the flash is recommended. Run ''sudo dd if=/dev/mtd0 of=backup.bin'' to create one. It can be restored with ''sudo flashcp backup.bin /dev/mtd0''. For recovery, creating a backup of the flash is recommended. Run ''sudo dd if=/dev/mtd0 of=backup.bin'' to create one. It can be restored with ''sudo flashcp backup.bin /dev/mtd0''.
  
-==== Unlocking U-Boot ==== +=== Unlocking U-Boot === 
-The password of U-Boot can be removed, though this step is optional. The following script will unlock U-Boot:+The password of U-Boot can be removed, though this step is optional. It is particularly useful for recovering the device through the serial port (i.e. booting an OpenWrt initramfs). The following script will unlock U-Boot:
  
 <code> <code>
Line 73: Line 80:
 </code> </code>
  
-==== Flashing OpenWRT ==== +=== Flashing OpenWRT === 
-After building OpenWRT, you should have a `.trx` file containing the kernel and ubifs. First we make sure the bootpartition is set to 0:+First we make sure the u-boot bootpartition is set to 0:
 <code> <code>
 echo '/dev/mtd2 0x0 0x1000 0x1000' > fw_env.config echo '/dev/mtd2 0x0 0x1000 0x1000' > fw_env.config
Line 80: Line 87:
 </code> </code>
  
-Now flash it with ''sudo flashcp squashfs-factory.trx /dev/mtd4''. Disconnect the Raspberry and boot the device. The first boot will take some time as it is resizing the UBIFS to fully span the partition. +Download the latest ''squashfs-factory.trx'' release, e.g. ''wget https://downloads.openwrt.org/snapshots/targets/ramips/mt7621/openwrt-ramips-mt7621-arcadyan_we420223-99-squashfs-factory.trx''
 +Now flash it with ''sudo flashcp openwrt-ramips-mt7621-arcadyan_we420223-99-squashfs-factory.trx /dev/mtd4''. Disconnect the flash chip from the Raspberry Pi, put the cooling block on and you are ready to test OpenWrt. The first boot will take some time as it is resizing the UBIFS to fully span the partition. You can connect a network cable to configure the device now, the IP is 192.168.1.1 and a DHCP server is enabled.
  
 ===== Debricking ===== ===== Debricking =====
Line 157: Line 164:
 ^ Interface Name   ^ Description                  ^ Default configuration    ^ ^ Interface Name   ^ Description                  ^ Default configuration    ^
 | br-lan           | LAN & WiFi                   | 192.168.1.1/24           | | br-lan           | LAN & WiFi                   | 192.168.1.1/24           |
-lan0             | Left port (viewed from back) | Attached to br-lan       | +swp0             | Left port (viewed from back) | Attached to br-lan       | 
-lan1             | Right port (viewed from back)| Attached to br-lan       |+swp1             | Right port (viewed from back)| Attached to br-lan       |
 | wlan0            | 2.4GHz WiFi                  | Disabled                 | | wlan0            | 2.4GHz WiFi                  | Disabled                 |
 | wlan1            | 5GHz WiFi                    | Disabled                 | | wlan1            | 5GHz WiFi                    | Disabled                 |
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   - Unscrew the two screws at the back.\\ {{:media:arcadyan:we420223-99_back.jpg?100|Back}}   - Unscrew the two screws at the back.\\ {{:media:arcadyan:we420223-99_back.jpg?100|Back}}
   - Open the case from bottom to top, so start separating the front and back next to the label, and work to the top. You'll find two clips on each side.\\ {{:media:arcadyan:we420223-99_opening_side.jpg?400}}   - Open the case from bottom to top, so start separating the front and back next to the label, and work to the top. You'll find two clips on each side.\\ {{:media:arcadyan:we420223-99_opening_side.jpg?400}}
-  - There is an internal clip at the top of the case, pop it.+  - There is an internal clip at the top of the case, pop it.\\ {{:media:arcadyan:we420223-99_internal_clip.jpg?400}}
  
 The heat sink can be unscrewed. There are thermal pads connecting the heat sink and cans, so pull gently when taking it off. With the heat sink removed, the antennas can also be disconnected. There is some glue on top of the antenna connectors which lets loose very easily. The heat sink can be unscrewed. There are thermal pads connecting the heat sink and cans, so pull gently when taking it off. With the heat sink removed, the antennas can also be disconnected. There is some glue on top of the antenna connectors which lets loose very easily.
Line 281: Line 288:
 This is the log from the not-latest firmware, the latest firmware disables the log in Linux. This is the log from the not-latest firmware, the latest firmware disables the log in Linux.
 <WRAP bootlog> <WRAP bootlog>
 +<nowiki>
 =================================================================== ===================================================================
       MT7621   stage1 code 10:33:55 (ASIC)       MT7621   stage1 code 10:33:55 (ASIC)
Line 1077: Line 1085:
 [00:00:39][bndstrg_periodic_exec]e[1;32mbndstrg->state=BNDSTRG_TBL_READY DUALBAND [00:00:39][bndstrg_periodic_exec]e[1;32mbndstrg->state=BNDSTRG_TBL_READY DUALBAND
 e[0mTime out! You may increase DEFAULT_TIMEOUT_COUNT[10]! e[0mTime out! You may increase DEFAULT_TIMEOUT_COUNT[10]!
 +</nowiki>
 </WRAP>\\ </WRAP>\\
  
 ==== OpenWrt bootlog ==== ==== OpenWrt bootlog ====
 <WRAP bootlog> <WRAP bootlog>
-<nowiki>COPY HERE THE BOOTLOG ONCE OPENWRT IS INSTALLED AND RUNNING</nowiki>+<nowiki> 
 +=================================================================== 
 +      MT7621   stage1 code 10:33:55 (ASIC) 
 +      CPU=500000000 HZ BUS=166666666 HZ 
 +================================================================== 
 +Change MPLL source from XTAL to CR... 
 +do MEMPLL setting.. 
 +MEMPLL Config : 0x11100000 
 +3PLL mode + External loopback 
 +=== XTAL-40Mhz === DDR-1200Mhz === 
 +PLL4 FB_DL: 0x3, 1/0 = 571/453 0D000000 
 +PLL3 FB_DL: 0x11, 1/0 = 600/424 45000000 
 +PLL2 FB_DL: 0x15, 1/0 = 611/413 55000000 
 +do DDR setting..[01F40000] 
 +Apply DDR3 Setting...(use customer AC) 
 +          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120 
 +      -------------------------------------------------------------------------------- 
 +0000:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0001:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0002:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0003:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0004:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0005:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0006:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
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 +0009:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +000A:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +000B:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +000C:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +000D:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    1 
 +000E:   0    0    0    0    0    0    0    0    0    1    1    1    1    1    1    1 
 +000F:   0    0    0    0    1    1    1    1    1    1    1    1    1    1    0    0 
 +0010:   1    1    1    1    1    1    1    1    1    0    0    0    0    0    0    0 
 +0011:   1    1    1    1    0    0    0    0    0    0    0    0    0    0    0    0 
 +0012:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0013:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0014:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0015:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0016:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0017:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0018:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +0019:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001A:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001B:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001C:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001D:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001E:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +001F:   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0 
 +rank 0 coarse = 15 
 +rank 0 fine = 72 
 +B:|    0    0    0    0    0    0    0    0    0    0    1    1    1    0    0    0 
 +opt_dle value:11 
 +DRAMC_R0DELDLY[018]=00001F1F 
 +================================================================== 
 + RX DQS perbit delay software calibration  
 +================================================================== 
 +1.0-15 bit dq delay value 
 +================================================================== 
 +bit|      1  2  3  4  5  6  7  8  9 
 +-------------------------------------- 
 +0 |    9 7 8 10 7 8 8 7 8 8  
 +10 |    9 10 9 12 9 10  
 +-------------------------------------- 
 + 
 +================================================================== 
 +2.dqs window 
 +x=pass dqs delay value (min~max)center  
 +y=0-7bit DQ of every group 
 +input delay:DQS0 =31 DQS1 = 31 
 +================================================================== 
 +bit DQS0 bit      DQS1 
 +0  (1~58)29  8  (1~58)29 
 +1  (1~58)29  9  (1~58)29 
 +2  (1~59)30  10  (1~60)30 
 +3  (1~60)30  11  (1~57)29 
 +4  (1~59)30  12  (1~60)30 
 +5  (1~60)30  13  (1~59)30 
 +6  (1~60)30  14  (1~61)31 
 +7  (1~61)31  15  (1~60)30 
 +================================================================== 
 +3.dq delay value last 
 +================================================================== 
 +bit|    0  1  2  3  4  5  6  7  8   9 
 +-------------------------------------- 
 +0 |    11 9 9 11 8 9 9 7 10 10  
 +10 |    10 12 10 13 9 11  
 +================================================================== 
 +================================================================== 
 +     TX  perbyte calibration  
 +================================================================== 
 +DQS loop = 15, cmp_err_1 = ffff0000  
 +dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1  
 +dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2  
 +DQ loop=15, cmp_err_1 = ffff00aa 
 +dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=1  
 +DQ loop=14, cmp_err_1 = ffff00a0 
 +DQ loop=13, cmp_err_1 = ffff0080 
 +DQ loop=12, cmp_err_1 = ffff0000 
 +dqs_perbyte_dly.last_dqdly_pass[0]=12,  finish count=2  
 +byte:0, (DQS,DQ)=(9,8) 
 +byte:1, (DQS,DQ)=(8,8) 
 +20,data:89 
 +[EMI] DRAMC calibration passed 
 + 
 +=================================================================== 
 +      MT7621   stage1 code done  
 +      CPU=500000000 HZ BUS=166666666 HZ 
 +=================================================================== 
 + 
 + 
 +U-Boot 1.1.3 (Dec  4 2017 - 11:37:57) 0.00 
 + 
 +Board: Ralink APSoC DRAM:  128 MB 
 +relocate_code Pointer at: 87f94000 
 + 
 +Config XHCI 40M PLL  
 +****************************** 
 +Software System Reset Occurred 
 +****************************** 
 +flash manufacture id: c2, device id 20 19 
 +find flash: MX25L25635E 
 +============================================  
 +Ralink UBoot Version: 5.0.0.1 
 +--------------------------------------------  
 +ASIC MT7621A DualCore (MAC to MT7530 Mode) 
 +DRAM_CONF_FROM: Auto-Detection  
 +DRAM_TYPE: DDR3  
 +DRAM bus: 16 bit 
 +Xtal Mode=3 OCP Ratio=1/3 
 +Flash component: 32 MBytes NOR Flash 
 +Date:Dec  4 2017  Time:11:37:57 
 +============================================  
 +icache: sets:256, ways:4, linesz:32 ,total:32768 
 +dcache: sets:256, ways:4, linesz:32 ,total:32768  
 + 
 + ##### The CPU freq = 880 MHZ ####  
 + estimate memory size =128 Mbytes 
 +#Reset_MT7530 
 +set LAN/WAN LLLLW 
 + 
 +Please choose the operation:  
 +   1: Load system code to SDRAM via TFTP.  
 +   2: Load system code then write to Flash via TFTP.  
 +   3: Boot system code via Flash (default). 
 +   4: Entr boot command line interface. 
 +   7: Load Boot Loader code then write to Flash via Serial.  
 +   9: Load Boot Loader code then write to Flash via TFTP.  
 +default: 3                                                                                                                                                                         0  
 +    
 +3: System Boot system code via Flash[0]. 
 +## Booting image at bc050000 ... 
 +old glbcfg partition is broken, magic=[0x23494255][0x55424923]! 
 +   Verifying Trx ... OK 
 +   Image Name:   MIPS OpenWrt Linux-5.10.161 
 +   Image Type:   MIPS Linux Kernel Image (uncompressed) 
 +   Data Size:    2692535 Bytes =  2.6 MB 
 +   Load Address: 80001000 
 +   Entry Point:  80001000 
 +   Verifying Checksum ... OK 
 +OK 
 +No initrd 
 +## Transferring control to Linux (at address 80001000) ... 
 +## Giving linux memsize in MB, 128 
 + 
 +Starting kernel ... 
 + 
 + 
 + 
 +OpenWrt kernel loader for MIPS based SoC 
 +Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> 
 +Decompressing kernel... done! 
 +Starting kernel at 80001000... 
 + 
 +[    0.000000] Linux version 5.10.161 (builder@buildhost) (mipsel-openwrt-linux-musl-gcc (OpenWrt GCC 11.3.0 r21603+2-fb15cb4ce9) 11.3.0, GNU ld (GNU Binutils) 2.37) #0 SMP Tue Dec 27 14:26:24 2022 
 +[    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3 
 +[    0.000000] printk: bootconsole [early0] enabled 
 +[    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc) 
 +[    0.000000] MIPS: machine is Arcadyan WE420223-99 
 +[    0.000000] Initrd not found or empty - disabling initrd 
 +[    0.000000] VPE topology {2,2} total 4 
 +[    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. 
 +[    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes 
 +[    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. 
 +[    0.000000] Zone ranges: 
 +[    0.000000]   Normal   [mem 0x0000000000000000-0x0000000007ffffff] 
 +[    0.000000]   HighMem  empty 
 +[    0.000000] Movable zone start for each node 
 +[    0.000000] Early memory node ranges 
 +[    0.000000]   node   0: [mem 0x0000000000000000-0x0000000007ffffff] 
 +[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff] 
 +[    0.000000] percpu: Embedded 15 pages/cpu s30480 r8192 d22768 u61440 
 +[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32480 
 +[    0.000000] Kernel command line: console=ttyS0,57600 ubi.mtd=5 root=/dev/ubiblock0_0 rootfstype=squashfs,jffs2 
 +[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear) 
 +[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear) 
 +[    0.000000] Writing ErrCtl register=00000000 
 +[    0.000000] Readback ErrCtl register=00000000 
 +[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off 
 +[    0.000000] Memory: 119472K/131072K available (7032K kernel code, 625K rwdata, 828K rodata, 1292K init, 243K bss, 11600K reserved, 0K cma-reserved, 0K highmem) 
 +[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 
 +[    0.000000] rcu: Hierarchical RCU implementation. 
 +[    0.000000] Tracing variant of Tasks RCU enabled. 
 +[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. 
 +[    0.000000] NR_IRQS: 256 
 +[    0.000000] CPU Clock: 880MHz 
 +[    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcaf478abb4, max_idle_ns: 440795247997 ns 
 +[    0.000013] sched_clock: 64 bits at 880MHz, resolution 1ns, wraps every 4398046511103ns 
 +[    0.015854] clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 4343773742 ns 
 +[    0.033809] Calibrating delay loop... 586.13 BogoMIPS (lpj=2930688) 
 +[    0.106131] pid_max: default: 32768 minimum: 301 
 +[    0.115443] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) 
 +[    0.129849] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) 
 +[    0.148140] rcu: Hierarchical SRCU implementation. 
 +[    0.157952] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build 
 +[    0.173529] smp: Bringing up secondary CPUs ... 
 +[    0.183279] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. 
 +[    0.183290] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes 
 +[    0.183301] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. 
 +[    0.183376] CPU1 revision is: 0001992f (MIPS 1004Kc) 
 +[    0.243361] Synchronize counters for CPU 1: done. 
 +[    0.305528] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. 
 +[    0.305537] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes 
 +[    0.305545] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. 
 +[    0.305593] CPU2 revision is: 0001992f (MIPS 1004Kc) 
 +[    0.364493] Synchronize counters for CPU 2: done. 
 +[    0.424841] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. 
 +[    0.424850] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes 
 +[    0.424858] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. 
 +[    0.424912] CPU3 revision is: 0001992f (MIPS 1004Kc) 
 +[    0.484074] Synchronize counters for CPU 3: done. 
 +[    0.543685] smp: Brought up 1 node, 4 CPUs 
 +[    0.556200] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns 
 +[    0.575716] futex hash table entries: 1024 (order: 3, 32768 bytes, linear) 
 +[    0.589534] pinctrl core: initialized pinctrl subsystem 
 +[    0.602231] NET: Registered protocol family 16 
 +[    0.612267] thermal_sys: Registered thermal governor 'step_wise' 
 +[    0.613296] cpuidle: using governor teo 
 +[    0.638657] rt2880-pinmux pinctrl: there is not valid maps for state default 
 +[    0.683299] clocksource: Switched to clocksource GIC 
 +[    0.695156] NET: Registered protocol family 2 
 +[    0.704010] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear) 
 +[    0.719695] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear) 
 +[    0.736368] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear) 
 +[    0.751484] TCP bind hash table entries: 1024 (order: 1, 8192 bytes, linear) 
 +[    0.765484] TCP: Hash tables configured (established 1024 bind 1024) 
 +[    0.778246] UDP hash table entries: 256 (order: 1, 8192 bytes, linear) 
 +[    0.791129] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear) 
 +[    0.805229] NET: Registered protocol family 1 
 +[    0.813806] PCI: CLS 0 bytes, default 32 
 +[    0.823874] workingset: timestamp_bits=14 max_order=15 bucket_order=1 
 +[    0.841029] squashfs: version 4.0 (2009/01/31) Phillip Lougher 
 +[    0.852578] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc. 
 +[    0.873035] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251) 
 +[    0.889474] mt7621_gpio 1e000600.gpio: registering 32 gpios 
 +[    0.900824] mt7621_gpio 1e000600.gpio: registering 32 gpios 
 +[    0.912094] mt7621_gpio 1e000600.gpio: registering 32 gpios 
 +[    0.923818] Serial: 8250/16550 driver, 16 ports, IRQ sharing enabled 
 +[    0.940573] printk: console [ttyS0] disabled 
 +[    0.949067] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 19, base_baud = 3125000) is a 16550A 
 +[    0.966996] printk: console [ttyS0] enabled 
 +[    0.966996] printk: console [ttyS0] enabled 
 +[    0.983535] printk: bootconsole [early0] disabled 
 +[    0.983535] printk: bootconsole [early0] disabled 
 +[    1.005547] spi-mt7621 1e000b00.spi: sys_freq: 220000000 
 +[    1.017892] spi-nor spi0.0: mx25l25635e (32768 Kbytes) 
 +[    1.028295] 12 fixed-partitions partitions found on MTD device spi0.0 
 +[    1.041148] Creating 12 MTD partitions on "spi0.0": 
 +[    1.050884] 0x000000000000-0x000002000000 : "ALL" 
 +[    1.061216] 0x000000000000-0x000000030000 : "Bootloader" 
 +[    1.072829] 0x000000030000-0x000000040000 : "Config" 
 +[    1.083807] 0x000000040000-0x000000050000 : "Factory" 
 +[    1.094885] 0x000000050000-0x000001fb0000 : "kernel" 
 +[    1.105803] 0x000000490000-0x000001fb0000 : "rootfs" 
 +[    1.116620] mtd: setting mtd5 (rootfs) as root device 
 +[    1.126800] mtdsplit: no squashfs found in "rootfs" 
 +[    1.136564] 0x000001000000-0x000001fb0000 : "Kernel2" 
 +[    1.147590] 0x000001440000-0x000001fb0000 : "RootFS2" 
 +[    1.158715] 0x000001fb0000-0x000001fc0000 : "glbcfg" 
 +[    1.169716] 0x000001fc0000-0x000001fd0000 : "board_data" 
 +[    1.181486] 0x000001fd0000-0x000001fe0000 : "glbcfg2" 
 +[    1.192745] 0x000001fe0000-0x000001ff0000 : "board_data2" 
 +[    1.254756] mt7530 mdio-bus:1f: MT7530 adapts as multi-chip module 
 +[    1.270802] mtk_soc_eth 1e100000.ethernet: generated random MAC address ca:db:70:e5:b0:70 
 +[    1.287960] mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 20 
 +[    1.304794] mtk_soc_eth 1e100000.ethernet: generated random MAC address 2e:72:0b:2d:99:3e 
 +[    1.321891] mtk_soc_eth 1e100000.ethernet swp0: mediatek frame engine at 0xbe100000, irq 20 
 +[    1.339883] i2c /dev entries driver 
 +[    1.349384] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges: 
 +[    1.362784] mt7621-pci 1e140000.pcie:   No bus range found for /pcie@1e140000, using [bus 00-ff] 
 +[    1.380312] mt7621-pci 1e140000.pcie:      MEM 0x0060000000..0x006fffffff -> 0x0000000000 
 +[    1.396622] mt7621-pci 1e140000.pcie:       IO 0x001e160000..0x001e16ffff -> 0x0000000000 
 +[    1.413013] mt7621-pci 1e140000.pcie: Parsing DT failed 
 +[    1.425752] NET: Registered protocol family 10 
 +[    1.436434] Segment Routing with IPv6 
 +[    1.443902] NET: Registered protocol family 17 
 +[    1.452830] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this. 
 +[    1.479010] 8021q: 802.1Q VLAN Support v1.8 
 +[    1.490791] mt7530 mdio-bus:1f: MT7530 adapts as multi-chip module 
 +[    1.523677] mt7530 mdio-bus:1f swp1 (uninitialized): PHY [mt7530-0:01] driver [MediaTek MT7530 PHY] (irq=25) 
 +[    1.547639] mt7530 mdio-bus:1f: configuring for fixed/rgmii link mode 
 +[    1.564450] DSA: tree 0 setup 
 +[    1.570659] rt2880-pinmux pinctrl: pcie is already enabled 
 +[    1.581673] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges: 
 +[    1.595051] mt7621-pci 1e140000.pcie:   No bus range found for /pcie@1e140000, using [bus 00-ff] 
 +[    1.612586] mt7621-pci 1e140000.pcie:      MEM 0x0060000000..0x006fffffff -> 0x0000000000 
 +[    1.628889] mt7621-pci 1e140000.pcie:       IO 0x001e160000..0x001e16ffff -> 0x0000000000 
 +[    1.645286] mt7621-pci-phy 1e149000.pcie-phy: PHY for 0xbe149000 (dual port = 1) 
 +[    1.660381] mt7621-pci-phy 1e14a000.pcie-phy: PHY for 0xbe14a000 (dual port = 0) 
 +[    1.675378] mt7621-pci 1e140000.pcie: failed to parse bus ranges property: -22 
 +[    1.790050] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz 
 +[    1.801174] mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz 
 +[    1.912472] mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK) 
 +[    1.926353] mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK) 
 +[    1.940216] mt7621-pci 1e140000.pcie: PCIE1 enabled 
 +[    1.949936] mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002 
 +[    1.968667] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00 
 +[    1.981341] pci_bus 0000:00: root bus resource [io  0x1e160000-0x1e16ffff] 
 +[    1.995051] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] 
 +[    2.008749] pci_bus 0000:00: root bus resource [bus 00-ff] 
 +[    2.019677] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff]) 
 +[    2.039991] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400 
 +[    2.051976] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x7fffffff] 
 +[    2.064478] pci 0000:00:00.0: reg 0x14: [mem 0x60200000-0x6020ffff] 
 +[    2.077024] pci 0000:00:00.0: supports D1 
 +[    2.085019] pci 0000:00:00.0: PME# supported from D0 D1 D3hot 
 +[    2.098149] pci 0000:01:00.0: [14c3:7615] type 00 class 0x000280 
 +[    2.110179] pci 0000:01:00.0: reg 0x10: initial BAR value 0x00000000 invalid 
 +[    2.124240] pci 0000:01:00.0: reg 0x10: [mem size 0x00100000 64bit] 
 +[    2.136901] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5.0 GT/s PCIe x1 link) 
 +[    2.167861] pci 0000:00:00.0: PCI bridge to [bus 01-ff] 
 +[    2.178292] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff] 
 +[    2.190442] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff] 
 +[    2.203976] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref] 
 +[    2.218363] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 
 +[    2.231590] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000] 
 +[    2.244779] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000] 
 +[    2.258646] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff] 
 +[    2.272171] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref] 
 +[    2.286563] pci 0000:00:00.0: BAR 1: assigned [mem 0x60200000-0x6020ffff] 
 +[    2.300089] pci 0000:00:00.0: BAR 7: assigned [io  0x1e160000-0x1e160fff] 
 +[    2.313628] pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x600fffff 64bit] 
 +[    2.328202] pci 0000:00:00.0: PCI bridge to [bus 01] 
 +[    2.338092] pci 0000:00:00.0:   bridge window [io  0x1e160000-0x1e160fff] 
 +[    2.351614] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff] 
 +[    2.365140] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref] 
 +[    2.380951] ubi0: attaching mtd5 
 +[    2.393603] mt7530 mdio-bus:1f: Link is Up - 1Gbps/Full - flow control rx/tx 
 +[    2.433220] ubi0: scanning is finished 
 +[    2.453234] ubi0: attached mtd5 (name "rootfs", size 27 MiB) 
 +[    2.464596] ubi0: PEB size: 65536 bytes (64 KiB), LEB size: 65408 bytes 
 +[    2.477780] ubi0: min./max. I/O unit sizes: 1/256, sub-page size 1 
 +[    2.490082] ubi0: VID header offset: 64 (aligned 64), data offset: 128 
 +[    2.503076] ubi0: good PEBs: 434, bad PEBs: 0, corrupted PEBs: 0 
 +[    2.515036] ubi0: user volume: 2, internal volumes: 1, max. volumes count: 128 
 +[    2.529420] ubi0: max/mean erase counter: 9/5, WL threshold: 4096, image sequence number: 1657914794 
 +[    2.547599] ubi0: available PEBs: 0, total reserved PEBs: 434, PEBs reserved for bad PEB handling: 0 
 +[    2.565816] ubi0: background thread "ubi_bgt0d" started, PID 459 
 +[    2.565936] UBI: block: volume size is not a multiple of 512, last 256 bytes are ignored! 
 +[    2.595279] block ubiblock0_0: created from ubi0:0(rootfs) 
 +[    2.614412] VFS: Mounted root (squashfs filesystem) readonly on device 254:0. 
 +[    2.632831] Freeing unused kernel memory: 1292K 
 +[    2.641888] This architecture does not have kernel memory protection. 
 +[    2.654743] Run /sbin/init as init process 
 +[    3.204027] init: Console is alive 
 +[    3.211196] init: - watchdog - 
 +[    4.225372] kmodloader: loading kernel modules from /etc/modules-boot.d/
 +[    4.347999] usbcore: registered new interface driver usbfs 
 +[    4.359202] usbcore: registered new interface driver hub 
 +[    4.369958] usbcore: registered new device driver usb 
 +[    4.389472] SCSI subsystem initialized 
 +[    4.427621] kmodloader: done loading kernel modules from /etc/modules-boot.d/
 +[    4.453721] init: - preinit - 
 +[    5.273772] random: jshn: uninitialized urandom read (4 bytes read) 
 +[    5.360807] random: jshn: uninitialized urandom read (4 bytes read) 
 +[    5.474410] random: jshn: uninitialized urandom read (4 bytes read) 
 +[    6.144296] mtk_soc_eth 1e100000.ethernet swp0: PHY [mdio-bus:00] driver [MediaTek MT7530 PHY] (irq=POLL) 
 +[    6.166211] mtk_soc_eth 1e100000.ethernet swp0: configuring for phy/rgmii link mode 
 +Press the [f] key and hit [enter] to enter failsafe mode 
 +Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level 
 +[    8.441218] UBIFS (ubi0:1): Mounting in unauthenticated mode 
 +[    8.452838] UBIFS (ubi0:1): background thread "ubifs_bgt0_1" started, PID 632 
 +[    8.485258] UBIFS (ubi0:1): recovery needed 
 +[    8.753298] random: crng init done 
 +[    8.760079] random: 7 urandom warning(s) missed due to ratelimiting 
 +[    9.206221] UBIFS (ubi0:1): recovery completed 
 +[    9.215286] UBIFS (ubi0:1): UBIFS: mounted UBI device 0, volume 1, name "rootfs_data" 
 +[    9.230902] UBIFS (ubi0:1): LEB size: 65408 bytes (63 KiB), min./max. I/O unit sizes: 8 bytes/256 bytes 
 +[    9.249636] UBIFS (ubi0:1): FS size: 21846272 bytes (20 MiB, 334 LEBs), journal size 1111936 bytes (1 MiB, 17 LEBs) 
 +[    9.270493] UBIFS (ubi0:1): reserved for root: 1031852 bytes (1007 KiB) 
 +[    9.283722] UBIFS (ubi0:1): media format: w5/r0 (latest is w5/r0), UUID 907AC48D-B261-4D78-B446-E51308CA2E7C, small LPT model 
 +[    9.471484] mount_root: overlay filesystem has not been fully initialized yet 
 +[    9.487468] mount_root: switching to ubifs overlay 
 +[    9.516608] urandom-seed: Seed file not found (/etc/urandom.seed) 
 +[    9.638014] procd: - early - 
 +[    9.644115] procd: - watchdog - 
 +[   10.293459] procd: - watchdog - 
 +[   10.395972] procd: - ubus - 
 +[   10.490686] procd: - init - 
 +Please press Enter to activate this console. 
 +[   11.278983] kmodloader: loading kernel modules from /etc/modules.d/
 +[   11.444820] urngd: v1.0.2 started. 
 +[   11.580561] Loading modules backported from Linux version v6.1-rc8-0-g76dcd734eca2 
 +[   11.595714] Backport generated by backports.git v5.15.81-1-41-g02e352527db5 
 +[   11.637751] xt_time: kernel timezone is -0000 
 +[   11.866609] mt7621-pci 1e140000.pcie: bus=1 slot=0 irq=22 
 +[   11.877437] pci 0000:00:00.0: enabling device (0006 -> 0007) 
 +[   11.888714] mt7615e 0000:01:00.0: enabling device (0000 -> 0002) 
 +[   11.993947] PPP generic driver version 2.4.2 
 +[   12.005458] NET: Registered protocol family 24 
 +[   12.014141] mt7615e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20180518100604a 
 +[   12.014141]  
 +[   12.046858] kmodloader: done loading kernel modules from /etc/modules.d/
 +[   12.268338] mt7615e 0000:01:00.0: N9 Firmware Version: _reserved_, Build Time: 20200814163649 
 +[   12.293499] mt7615e 0000:01:00.0: CR4 Firmware Version: _reserved_, Build Time: 20190415154149 
 +[   29.833747] mtk_soc_eth 1e100000.ethernet swp0: PHY [mdio-bus:00] driver [MediaTek MT7530 PHY] (irq=POLL) 
 +[   29.857310] mtk_soc_eth 1e100000.ethernet swp0: configuring for phy/rgmii link mode 
 +[   29.875310] br-lan: port 1(swp0) entered blocking state 
 +[   29.885831] br-lan: port 1(swp0) entered disabled state 
 +[   29.897080] device swp0 entered promiscuous mode 
 +[   29.933630] mtk_soc_eth 1e100000.ethernet eth0: configuring for fixed/rgmii link mode 
 +[   29.950170] mtk_soc_eth 1e100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx 
 +[   29.968455] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready 
 +[   29.983949] device eth0 entered promiscuous mode 
 +[   29.993952] mt7530 mdio-bus:1f swp1: configuring for phy/gmii link mode 
 +[   30.007840] 8021q: adding VLAN 0 to HW filter on device swp1 
 +[   30.023050] br-lan: port 2(swp1) entered blocking state 
 +[   30.033624] br-lan: port 2(swp1) entered disabled state 
 +[   30.045040] device swp1 entered promiscuous mode 
 +</nowiki>
 </WRAP>\\ </WRAP>\\
  
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  • Last modified: 2024/03/20 17:28
  • by harm