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| inbox:toh:arcadyan:astoria:we420223-99 [2022/10/09 13:14] – [Table] WIP harm | inbox:toh:arcadyan:astoria:we420223-99 [2023/05/18 16:51] – [Flashing via the original web interface] Fix list harm | ||
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| ====== Arcadyan WE420223-99 ====== | ====== Arcadyan WE420223-99 ====== | ||
| - | ~~NOTOC~~ | ||
| - | |||
| - | /* This template is intended to be used via https:// | ||
| - | |||
| - | {{page> | ||
| - | |||
| - | //Write a short, relevant description of the device. Include a technical overview, but avoid marketing buzzwords/ | ||
| - | |||
| The Arcadyan WE420223-99 is an access point distributed by KPN in the Netherlands under the name " | The Arcadyan WE420223-99 is an access point distributed by KPN in the Netherlands under the name " | ||
| Line 15: | Line 7: | ||
| ===== OpenWrt support ===== | ===== OpenWrt support ===== | ||
| - | Official support | + | There is no stable release yet that supports this device, there are snapshot releases though. |
| - | * Patchwork patch: https:// | ||
| - | * GitHub fork: https:// | ||
| * OpenWrt forum thread: https:// | * OpenWrt forum thread: https:// | ||
| * Tweakers forum thread: https:// | * Tweakers forum thread: https:// | ||
| Line 31: | Line 21: | ||
| Both Ethernet ports are individually connected to the CPU by default. This allows for gigabit routing speeds but decreases switching speed as data is passed through the CPU. By reverting [[https:// | Both Ethernet ports are individually connected to the CPU by default. This allows for gigabit routing speeds but decreases switching speed as data is passed through the CPU. By reverting [[https:// | ||
| - | /*** if info available: uncomment and fill in | + | |
| ===== Installation ===== | ===== Installation ===== | ||
| - | - → [[: | + | If you are running an old firmware |
| - | - → [[docs: | + | |
| - | - → [[: | + | |
| - | ==== Installing OpenWrt ==== | + | Otherwise, we need to directly write to the flash chip since the official firmware' |
| - | ***/ | + | |
| + | ==== Flashing via the original web interface ==== | ||
| + | |||
| + | The original firmware requires signed firmware. The code to do so is on GitHub: https:// | ||
| + | |||
| + | - Flash the signed image via the web interface. OpenWRT should boot and start a DHCP server. | ||
| + | - Go to http:// | ||
| + | - Profit! You might still want to unlock the U-Boot password for recovery in the future (see below) | ||
| + | ==== Writing directly to the flash chip ==== | ||
| + | === Connecting the flash chip to a Raspberry Pi === | ||
| + | A Raspberry Pi can be used to program the flash chip in-circuit (thanks FPSUsername for discovering). On the Raspberry Pi, install '' | ||
| + | Enable it in ''/ | ||
| + | |||
| + | Connect the chip directly to the Raspberry Pi's SPI pins. Use the following connections: | ||
| + | |||
| + | {{: | ||
| + | |||
| + | ^ Flash Chip ^ Raspberry Pi ^ | ||
| + | | VCC | 3v3 | | ||
| + | | RESET | 3v3 | | ||
| + | | /CS | GPIO 8 (SPI0 CE0) | | ||
| + | | DO | GPIO 9 (SPI0 MISO) | | ||
| + | | CLK | GPIO11 (SPI0 SCLK) | | ||
| + | | DI | GPIO 10 (SPI0 MOSI) | | ||
| + | | GND | Ground | ||
| + | |||
| + | You can solder wires to the flash chip but using a [[https:// | ||
| + | |||
| + | After connecting the flash chip and rebooting, the ''/ | ||
| + | |||
| + | === Creating a backup === | ||
| + | For recovery, creating a backup of the flash is recommended. Run '' | ||
| + | |||
| + | === Unlocking U-Boot === | ||
| + | The password of U-Boot can be removed, though this step is optional. It is particularly useful for recovering the device through the serial port (i.e. booting an OpenWrt initramfs). The following script will unlock U-Boot: | ||
| + | |||
| + | < | ||
| + | #!/bin/bash | ||
| + | sudo dd if=/ | ||
| + | |||
| + | # these winbond or mxc u-boot variants are known to work | ||
| + | echo ' | ||
| + | echo ' | ||
| + | |||
| + | if [ $? -ne 0 ]; then | ||
| + | echo " | ||
| + | exit 1 | ||
| + | fi | ||
| + | |||
| + | cp bootloader_original.bin bootloader_patched.bin | ||
| + | echo '00 00 02 24 08 00 e0 03 00 00 00 00 ' | xxd -r -p | dd conv=notrunc of=bootloader_patched.bin seek=$((0x1420)) bs=1 | ||
| + | sudo flashcp bootloader_patched.bin /dev/mtd1 | ||
| + | </ | ||
| + | |||
| + | === Flashing OpenWRT === | ||
| + | First we make sure the u-boot bootpartition is set to 0: | ||
| + | < | ||
| + | echo '/ | ||
| + | sudo fw_setenv -c fw_env.config bootpartition 0 | ||
| + | </ | ||
| + | |||
| + | Download the latest '' | ||
| + | Now flash it with '' | ||
| - | /*** if info available: uncomment and fill in | ||
| ===== Debricking ===== | ===== Debricking ===== | ||
| - | -> [[docs: | + | When U-Boot's password protection has been removed, OpenWRT can be loaded from TFTP. Alternatively, |
| - | ***/ | + | |
| + | Start a TFTP server containing the `initramfs-kernel.bin` file on IP 192.168.11.2. Then, run this '' | ||
| + | |||
| + | <code> | ||
| + | # | ||
| + | |||
| + | # Serial port setup. | ||
| + | set line / | ||
| + | set serial 8n1 | ||
| + | set speed 57600 | ||
| + | |||
| + | # General C-Kermit settings. | ||
| + | set flow-control none | ||
| + | set file type bin | ||
| + | set carrier-watch off | ||
| + | set prefixing all | ||
| + | set modem none | ||
| + | |||
| + | echo " | ||
| + | |||
| + | input 60 " | ||
| + | input 9 " | ||
| + | IF FAIL EXIT 1 | ||
| + | output " | ||
| + | |||
| + | input 10 " | ||
| + | IF FAIL EXIT 1 | ||
| + | # patch trx check function | ||
| + | lineout "mm.l 87fa7600" | ||
| + | input 2 " | ||
| + | IF FAIL EXIT 1 | ||
| + | lineout " | ||
| + | input 2 " | ||
| + | IF FAIL EXIT 1 | ||
| + | lineout " | ||
| + | input 2 " | ||
| + | IF FAIL EXIT 1 | ||
| + | lineout " | ||
| + | input 2 " | ||
| + | IF FAIL EXIT 1 | ||
| + | output \3 | ||
| + | input 10 " | ||
| + | |||
| + | lineout " | ||
| + | input 60 " | ||
| + | lineout bootm 85001000 | ||
| + | |||
| + | connect | ||
| + | </code> | ||
| + | This script patches the TRX verification code as it does not work here. | ||
| + | Once you are in OpenWRT you can add it to your network with the '' | ||
| /*** if info available: uncomment and fill in | /*** if info available: uncomment and fill in | ||
| Line 66: | Line 164: | ||
| ^ Interface Name ^ Description | ^ Interface Name ^ Description | ||
| | br-lan | | br-lan | ||
| - | | lan0 | Left port (viewed from back) | Attached to br-lan | + | | swp0 | Left port (viewed from back) | Attached to br-lan |
| - | | lan1 | Right port (viewed from back)| Attached to br-lan | + | | swp1 | Right port (viewed from back)| Attached to br-lan |
| | wlan0 | 2.4GHz WiFi | Disabled | | wlan0 | 2.4GHz WiFi | Disabled | ||
| | wlan1 | 5GHz WiFi | Disabled | | wlan1 | 5GHz WiFi | Disabled | ||
| Line 93: | Line 191: | ||
| ==== Flash Layout ==== | ==== Flash Layout ==== | ||
| - | <WRAP BOX> | ||
| - | FIXME // | ||
| - | Please check out the article | + | ^ Arcadyan WE420223-99 OpenWRT Flash Layout |
| - | </WRAP> | + | ^ Layer0 |
| + | ^ Layer1 | ||
| + | ^ Layer2 | ||
| + | ^ filesystem | ||
| + | ^ Layer3 | ||
| + | ^ Name | | | | | ||
| + | ^ <color magenta> | ||
| + | ^ filesystem | ||
| + | | Description | ||
| - | ^ Arcadyan WE420223-99 OpenWRT Flash Layout | + | Which the Kernel logs as: |
| - | ^ Layer0 | + | < |
| - | ^ Layer1 | + | 0x000000000000-0x000002000000 : " |
| - | ^ Layer2 | + | 0x000000000000-0x000000030000 |
| - | ^ <color magenta> | + | 0x000000030000-0x000000040000 : " |
| - | ^ filesystem | + | 0x000000040000-0x000000050000 : "Factory" |
| - | ^ Layer3 | + | 0x000000050000-0x000001fb0000 : "kernel" |
| - | ^ Size in KiB | + | 0x000000490000-0x000001fb0000 : "rootfs" |
| - | ^ Name | | | | | + | 0x000001000000-0x000001fb0000 : " |
| - | ^ <color magenta> | + | 0x000001440000-0x000001fb0000 |
| - | ^ filesystem | + | 0x000001fb0000-0x000001fc0000 |
| - | | Description | + | 0x000001fc0000-0x000001fd0000 : " |
| + | 0x000001fd0000-0x000001fe0000 : " | ||
| + | 0x000001fe0000-0x000001ff0000 : " | ||
| + | </code> | ||
| + | The original firmware used an A/B partitioning scheme for updating, hence the '' | ||
| + | < | ||
| + | 0x000000000000-0x000002000000 : " | ||
| + | 0x000000000000-0x000000030000 : " | ||
| + | 0x000000030000-0x000000040000 : " | ||
| + | 0x000000040000-0x000000050000 : " | ||
| + | 0x000000050000-0x000001000000 : " | ||
| + | 0x0000002bc17c-0x000001000000 : " | ||
| + | mtd: partition " | ||
| + | 0x000001000000-0x000001fb0000 : " | ||
| + | 0x00000126c4dc-0x000001fb0000 : " | ||
| + | mtd: partition " | ||
| + | 0x000001fb0000-0x000001fc0000 : " | ||
| + | 0x000001fc0000-0x000001fd0000 : " | ||
| + | 0x000001fd0000-0x000001fe0000 : " | ||
| + | 0x000001fe0000-0x000001ff0000 : " | ||
| + | </ | ||
| + | It looks like the original Linux dynamically calculates the offset of RootFS (squashfs filesystem). The '' | ||
| + | |||
| + | === Dual-booting === | ||
| + | The '' | ||
| + | |||
| + | OpenWRT cannot be stored on ''/ | ||
| ==== Photos ==== | ==== Photos ==== | ||
| - | /* =====>>>>> | + | {{:media: |
| - | /* When uploading photos, **name them** intelligently. Nobody knows what 20100930_000602.jpg is! */ | + | {{:media:arcadyan:we420223-99_back.jpg?400|Back}} |
| - | /* e.g. {{:media:yourbrand:yourbrand_yourmodel_front.jpg? | + | |
| - | /* Thanks, your wiki administration - Oct. 2015 */ | + | |
| - | **Insert photo of front of the casing** | + | {{: |
| - | **Insert photo of back of the casing** | + | {{: |
| - | **Insert photo of backside label** | + | === Macronix variant === |
| + | {{media: | ||
| + | {{media: | ||
| - | **Insert photo of PCB** | + | === Winbond variant === |
| + | {{media: | ||
| + | {{media: | ||
| ==== Opening the case ==== | ==== Opening the case ==== | ||
| + | - Unscrew the two screws at the back.\\ {{: | ||
| + | - Open the case from bottom to top, so start separating the front and back next to the label, and work to the top. You'll find two clips on each side.\\ {{: | ||
| + | - There is an internal clip at the top of the case, pop it.\\ {{: | ||
| + | |||
| + | The heat sink can be unscrewed. There are thermal pads connecting the heat sink and cans, so pull gently when taking it off. With the heat sink removed, the antennas can also be disconnected. There is some glue on top of the antenna connectors which lets loose very easily. | ||
| - | <WRAP BOX> | ||
| - | FIXME //Describe what needs to be done to open the device, e.g. remove rubber feet, adhesive labels, screws, ...// | ||
| - | </ | ||
| ==== Serial ==== | ==== Serial ==== | ||
| - | -> [[docs: | + | The [[docs: |
| - | How to connect to the Serial Port of this specific device:\\ | + | {{:media: |
| - | **Insert photo of PCB with markings for serial port** | + | |
| - | <WRAP BOX> | + | ^ Serial connection parameters | 57600, 8N1, 3.3V | |
| - | FIXME //Replace EXAMPLE by real values.// | + | |
| - | </ | + | |
| - | ^ Serial connection parameters\\ for Arcadyan / Astoria WE420223-99 @@Version@@ | EXAMPLE 115200, 8N1, 3.3V | | + | Note that with cheap serial adapters, you might need to disconnect the serial adapter when resetting the device. |
| + | /*** if info available: uncomment and fill in | ||
| ==== JTAG ==== | ==== JTAG ==== | ||
| -> [[docs: | -> [[docs: | ||
| Line 151: | Line 283: | ||
| How to connect to the JTAG Port of this specific device:\\ | How to connect to the JTAG Port of this specific device:\\ | ||
| **Insert photo of PCB with markings for JTAG port** | **Insert photo of PCB with markings for JTAG port** | ||
| + | ***/ | ||
| ===== Bootlogs ===== | ===== Bootlogs ===== | ||
| ==== OEM bootlog ==== | ==== OEM bootlog ==== | ||
| + | This is the log from the not-latest firmware, the latest firmware disables the log in Linux. | ||
| <WRAP bootlog> | <WRAP bootlog> | ||
| - | < | + | < |
| + | =================================================================== | ||
| + | | ||
| + | | ||
| + | ================================================================== | ||
| + | Change MPLL source from XTAL to CR... | ||
| + | do MEMPLL setting.. | ||
| + | MEMPLL Config : 0x11100000 | ||
| + | 3PLL mode + External loopback | ||
| + | === XTAL-40Mhz === DDR-1200Mhz === | ||
| + | PLL4 FB_DL: 0x7, 1/0 = 627/397 1D000000 | ||
| + | PLL3 FB_DL: 0x12, 1/0 = 657/367 49000000 | ||
| + | PLL2 FB_DL: 0x17, 1/0 = 595/429 5D000000 | ||
| + | do DDR setting..[01F40000] | ||
| + | Apply DDR3 Setting...(use customer AC) | ||
| + | 0 8 | ||
| + | -------------------------------------------------------------------------------- | ||
| + | 0000: | ||
| + | 0001: | ||
| + | 0002: | ||
| + | 0003: | ||
| + | 0004: | ||
| + | 0005: | ||
| + | 0006: | ||
| + | 0007: | ||
| + | 0008: | ||
| + | 0009: | ||
| + | 000A: | ||
| + | 000B: | ||
| + | 000C: | ||
| + | 000D: | ||
| + | 000E: | ||
| + | 000F: | ||
| + | 0010: | ||
| + | 0011: | ||
| + | 0012: | ||
| + | 0013: | ||
| + | 0014: | ||
| + | 0015: | ||
| + | 0016: | ||
| + | 0017: | ||
| + | 0018: | ||
| + | 0019: | ||
| + | 001A: | ||
| + | 001B: | ||
| + | 001C: | ||
| + | 001D: | ||
| + | 001E: | ||
| + | 001F: | ||
| + | rank 0 coarse = 15 | ||
| + | rank 0 fine = 72 | ||
| + | B:| 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 | ||
| + | opt_dle value:8 | ||
| + | DRAMC_R0DELDLY[018]=00001E1F | ||
| + | ================================================================== | ||
| + | RX DQS perbit delay software calibration | ||
| + | ================================================================== | ||
| + | 1.0-15 bit dq delay value | ||
| + | ================================================================== | ||
| + | bit| | ||
| + | -------------------------------------- | ||
| + | 0 | 9 7 8 9 7 7 8 7 8 8 | ||
| + | 10 | 9 10 9 12 9 10 | ||
| + | -------------------------------------- | ||
| + | |||
| + | ================================================================== | ||
| + | 2.dqs window | ||
| + | x=pass dqs delay value (min~max)center | ||
| + | y=0-7bit DQ of every group | ||
| + | input delay:DQS0 =31 DQS1 = 30 | ||
| + | ================================================================== | ||
| + | bit DQS0 bit DQS1 | ||
| + | 0 (1~60)30 | ||
| + | 1 (1~60)30 | ||
| + | 2 (1~60)30 | ||
| + | 3 (1~58)29 | ||
| + | 4 (1~58)29 | ||
| + | 5 (1~60)30 | ||
| + | 6 (1~59)30 | ||
| + | 7 (1~62)31 | ||
| + | ================================================================== | ||
| + | 3.dq delay value last | ||
| + | ================================================================== | ||
| + | bit| 0 1 2 3 4 5 6 7 8 9 | ||
| + | -------------------------------------- | ||
| + | 0 | 10 8 9 11 9 8 9 7 8 9 | ||
| + | 10 | 9 12 10 12 9 10 | ||
| + | ================================================================== | ||
| + | ================================================================== | ||
| + | | ||
| + | ================================================================== | ||
| + | DQS loop = 15, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[0]=15, | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[1]=15, | ||
| + | DQ loop=15, cmp_err_1 = ffff00a2 | ||
| + | dqs_perbyte_dly.last_dqdly_pass[1]=15, | ||
| + | DQ loop=14, cmp_err_1 = ffff00a0 | ||
| + | DQ loop=13, cmp_err_1 = ffff0080 | ||
| + | DQ loop=12, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqdly_pass[0]=12, | ||
| + | byte:0, (DQS, | ||
| + | byte:1, (DQS, | ||
| + | 20, | ||
| + | [EMI] DRAMC calibration passed | ||
| + | |||
| + | =================================================================== | ||
| + | | ||
| + | | ||
| + | =================================================================== | ||
| + | |||
| + | |||
| + | U-Boot 1.1.3 (Dec 4 2017 - 11:37:57) 0.00 | ||
| + | |||
| + | Board: Ralink APSoC DRAM: 128 MB | ||
| + | relocate_code Pointer at: 87f94000 | ||
| + | |||
| + | Config XHCI 40M PLL | ||
| + | flash manufacture id: c2, device id 20 19 | ||
| + | find flash: MX25L25635E | ||
| + | ============================================ | ||
| + | Ralink UBoot Version: 5.0.0.1 | ||
| + | -------------------------------------------- | ||
| + | ASIC MT7621A DualCore (MAC to MT7530 Mode) | ||
| + | DRAM_CONF_FROM: | ||
| + | DRAM_TYPE: DDR3 | ||
| + | DRAM bus: 16 bit | ||
| + | Xtal Mode=3 OCP Ratio=1/3 | ||
| + | Flash component: 32 MBytes NOR Flash | ||
| + | Date: | ||
| + | ============================================ | ||
| + | icache: sets:256, ways:4, linesz:32 , | ||
| + | dcache: sets:256, ways:4, linesz:32 , | ||
| + | |||
| + | ##### The CPU freq = 880 MHZ #### | ||
| + | | ||
| + | # | ||
| + | set LAN/WAN LLLLW | ||
| + | |||
| + | Please choose the operation: | ||
| + | 1: Load system code to SDRAM via TFTP. | ||
| + | 2: Load system code then write to Flash via TFTP. | ||
| + | 3: Boot system code via Flash (default). | ||
| + | 4: Entr boot command line interface. | ||
| + | 7: Load Boot Loader code then write to Flash via Serial. | ||
| + | 9: Load Boot Loader code then write to Flash via TFTP. | ||
| + | default: 3 | ||
| + | | ||
| + | |||
| + | 3: System Boot system code via Flash[1]. | ||
| + | ## Booting image at bd000000 ... | ||
| + | cur glbcfg partition 1 is good! | ||
| + | | ||
| + | Image Name: Linux Kernel Image | ||
| + | Image Type: MIPS Linux Kernel Image (lzma compressed) | ||
| + | Data Size: 2540670 Bytes = 2.4 MB | ||
| + | Load Address: 81001000 | ||
| + | Entry Point: | ||
| + | | ||
| + | | ||
| + | No initrd | ||
| + | ## Transferring control to Linux (at address 814df880) ... | ||
| + | ## Giving linux memsize in MB, 128 | ||
| + | |||
| + | Starting kernel ... | ||
| + | LINUX started... | ||
| + | |||
| + | THIS IS ASIC | ||
| + | |||
| + | SDK 5.0.S.0 | ||
| + | Linux version 3.10.14 (william_chen@sw1.2) (gcc version 4.6.3 (Buildroot 2012.11.1) ) #1 SMP Thu Aug 16 17:16:55 CST 2018 | ||
| + | |||
| + | The CPU feqenuce set to 880 MHz | ||
| + | GCMP present | ||
| + | CPU0 revision is: 0001992f (MIPS 1004Kc) | ||
| + | Software DMA cache coherency | ||
| + | Determined physical RAM map: | ||
| + | | ||
| + | Zone ranges: | ||
| + | DMA [mem 0x00000000-0x00ffffff] | ||
| + | Normal | ||
| + | Movable zone start for each node | ||
| + | Early memory node ranges | ||
| + | node 0: [mem 0x00000000-0x07ffffff] | ||
| + | Detected 3 available secondary CPU(s) | ||
| + | Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes. | ||
| + | Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | PERCPU: Embedded 7 pages/cpu @8186e000 s6528 r8192 d13952 u32768 | ||
| + | Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 | ||
| + | Kernel command line: console=ttyS1, | ||
| + | PID hash table entries: 512 (order: -1, 2048 bytes) | ||
| + | Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) | ||
| + | Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) | ||
| + | Writing ErrCtl register=0006b811 | ||
| + | Readback ErrCtl register=0006b811 | ||
| + | Memory: 122216k/ | ||
| + | Hierarchical RCU implementation. | ||
| + | NR_IRQS: | ||
| + | console [ttyS1] enabled | ||
| + | Calibrating delay loop... 574.46 BogoMIPS (lpj=1148928) | ||
| + | pid_max: default: 32768 minimum: 301 | ||
| + | Mount-cache hash table entries: 512 | ||
| + | launch: starting cpu1 | ||
| + | launch: cpu1 gone! | ||
| + | CPU1 revision is: 0001992f (MIPS 1004Kc) | ||
| + | Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes. | ||
| + | Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | Synchronize counters for CPU 1: done. | ||
| + | launch: starting cpu2 | ||
| + | launch: cpu2 gone! | ||
| + | CPU2 revision is: 0001992f (MIPS 1004Kc) | ||
| + | Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes. | ||
| + | Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | Synchronize counters for CPU 2: done. | ||
| + | launch: starting cpu3 | ||
| + | launch: cpu3 gone! | ||
| + | CPU3 revision is: 0001992f (MIPS 1004Kc) | ||
| + | Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes. | ||
| + | Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | Synchronize counters for CPU 3: done. | ||
| + | Brought up 4 CPUs | ||
| + | devtmpfs: initialized | ||
| + | NET: Registered protocol family 16 | ||
| + | release PCIe RST: RALINK_RSTCTRL = 7000000 | ||
| + | PCIE PHY initialize | ||
| + | ***** Xtal 40MHz ***** | ||
| + | start MT7621 PCIe register access | ||
| + | RALINK_RSTCTRL = 7000000 | ||
| + | RALINK_CLKCFG1 = 77ffeff8 | ||
| + | |||
| + | *************** MT7621 PCIe RC mode ************* | ||
| + | PCIE0 no card, disable it(RST& | ||
| + | PCIE2 no card, disable it(RST& | ||
| + | pcie_link status = 0x2 | ||
| + | RALINK_RSTCTRL= 2000000 | ||
| + | *** Configure Device number setting of Virtual PCI-PCI bridge *** | ||
| + | RALINK_PCI_PCICFG_ADDR = 21007f2 -> 20107f2 | ||
| + | PCIE1 enabled | ||
| + | interrupt enable status: 200000 | ||
| + | Port 0 N_FTS = 1b105000 | ||
| + | config reg done | ||
| + | init_rt2880pci done | ||
| + | bio: create slab < | ||
| + | PCI host bridge to bus 0000:00 | ||
| + | pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] | ||
| + | pci_bus 0000:00: root bus resource [io 0x1e160000-0x1e16ffff] | ||
| + | pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | pci 0000: | ||
| + | PCI: Enabling device 0000: | ||
| + | BAR0 at slot 0 = 0 | ||
| + | bus=0x0, slot = 0x0 | ||
| + | res[0]-> | ||
| + | res[0]-> | ||
| + | res[1]-> | ||
| + | res[1]-> | ||
| + | res[2]-> | ||
| + | res[2]-> | ||
| + | res[3]-> | ||
| + | res[3]-> | ||
| + | res[4]-> | ||
| + | res[4]-> | ||
| + | res[5]-> | ||
| + | res[5]-> | ||
| + | bus=0x1, slot = 0x0, irq=0x18 | ||
| + | res[0]-> | ||
| + | res[0]-> | ||
| + | res[1]-> | ||
| + | res[1]-> | ||
| + | res[2]-> | ||
| + | res[2]-> | ||
| + | res[3]-> | ||
| + | res[3]-> | ||
| + | res[4]-> | ||
| + | res[4]-> | ||
| + | res[5]-> | ||
| + | res[5]-> | ||
| + | Switching to clocksource Ralink Systick timer | ||
| + | NET: Registered protocol family 2 | ||
| + | Clockevents: | ||
| + | Clockevents: | ||
| + | Clockevents: | ||
| + | MIPS is not functional. | ||
| + | MIPS is not functional. | ||
| + | Clockevents: | ||
| + | Could not switch to high resolution mode on CPU 1 | ||
| + | Could not switch to high resolution mode on CPU 2 | ||
| + | Could not switch to high resolution mode on CPU 3 | ||
| + | MIPS is not functional. | ||
| + | Could not switch to high resolution mode on CPU 0 | ||
| + | TCP established hash table entries: 1024 (order: 1, 8192 bytes) | ||
| + | TCP bind hash table entries: 1024 (order: 1, 8192 bytes) | ||
| + | TCP: Hash tables configured (established 1024 bind 1024) | ||
| + | TCP: reno registered | ||
| + | UDP hash table entries: 256 (order: 1, 8192 bytes) | ||
| + | UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) | ||
| + | NET: Registered protocol family 1 | ||
| + | 4 CPUs re-calibrate udelay(lpj = 1167360) | ||
| + | squashfs: version 4.0 (2009/ | ||
| + | msgmni has been set to 238 | ||
| + | io scheduler noop registered (default) | ||
| + | reg_int_mask=0, | ||
| + | HSDMA_init | ||
| + | |||
| + | | ||
| + | |||
| + | | ||
| + | TX_CTX_IDX0 = 0 | ||
| + | TX_DTX_IDX0 = 0 | ||
| + | RX_CRX_IDX0 = 3ff | ||
| + | RX_DRX_IDX0 = 0 | ||
| + | set_fe_HSDMA_glo_cfg | ||
| + | HSDMA_GLO_CFG = 465 | ||
| + | Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled | ||
| + | serial8250: ttyS0 at MMIO 0x1e000d00 (irq = 27) is a 16550A | ||
| + | serial8250: ttyS1 at MMIO 0x1e000c00 (irq = 26) is a 16550A | ||
| + | Ralink gpio driver initialized | ||
| + | flash manufacture id: c2, device id 20 19 | ||
| + | MX25L25635E(c2 2019c220) (32768 Kbytes) | ||
| + | mtd .name = raspi, .size = 0x02000000 (32M) .erasesize = 0x00010000 (64K) .numeraseregions = 0 | ||
| + | in find_rootfs_mtd_partitions | ||
| + | The trx header | ||
| + | raspi: squash filesystem found at offset 0x002bc17c | ||
| + | Found image1 partition off 0x002bc17c size 0x00d43e84 | ||
| + | in find_rootfs_mtd_partitions | ||
| + | The trx header | ||
| + | raspi: squash filesystem found at offset 0x0126c4dc | ||
| + | Found image2 partition off 0x0126c4dc size 0x00d43b24 | ||
| + | Creating 12 MTD partitions on " | ||
| + | 0x000000000000-0x000002000000 : " | ||
| + | 0x000000000000-0x000000030000 : " | ||
| + | 0x000000030000-0x000000040000 : " | ||
| + | 0x000000040000-0x000000050000 : " | ||
| + | 0x000000050000-0x000001000000 : " | ||
| + | 0x0000002bc17c-0x000001000000 : " | ||
| + | mtd: partition " | ||
| + | 0x000001000000-0x000001fb0000 : " | ||
| + | 0x00000126c4dc-0x000001fb0000 : " | ||
| + | mtd: partition " | ||
| + | 0x000001fb0000-0x000001fc0000 : " | ||
| + | 0x000001fc0000-0x000001fd0000 : " | ||
| + | 0x000001fd0000-0x000001fe0000 : " | ||
| + | 0x000001fe0000-0x000001ff0000 : " | ||
| + | PPP generic driver version 2.4.2 | ||
| + | PPP BSD Compression module registered | ||
| + | NET: Registered protocol family 24 | ||
| + | register mt_drv | ||
| + | |||
| + | |||
| + | === pAd = c0181000, size = 3788464 === | ||
| + | |||
| + | <-- RTMPAllocAdapterBlock, | ||
| + | pAd-> | ||
| + | RTMPInitPCIeDevice(): | ||
| + | DriverOwn():: | ||
| + | DriverOwn():: | ||
| + | mt_pci_chip_cfg(): | ||
| + | mt_pci_chip_cfg(): | ||
| + | RtmpChipOpsHook(492): | ||
| + | mt7615_init()--> | ||
| + | Use the default ePAeLNA bin image! | ||
| + | Use the default / | ||
| + | < | ||
| + | ChipOpsMCUHook | ||
| + | cut_through_token_list_init(): | ||
| + | cut_through_token_list_init(): | ||
| + | cut_through_token_list_init(): | ||
| + | cut_through_token_list_init(): | ||
| + | <-- RTMPAllocTxRxRingMemory, | ||
| + | rdm_major = 253 | ||
| + | GMAC1_MAC_ADRH -- : 0x0000000c | ||
| + | GMAC1_MAC_ADRL -- : 0x432880a8 | ||
| + | Ralink APSoC Ethernet Driver Initilization. v3.1 1024 rx/tx descriptors allocated, mtu = 1500! | ||
| + | GMAC1_MAC_ADRH -- : 0x0000000c | ||
| + | GMAC1_MAC_ADRL -- : 0x432880a8 | ||
| + | PROC INIT OK! | ||
| + | TCP: cubic registered | ||
| + | Initializing XFRM netlink socket | ||
| + | NET: Registered protocol family 10 | ||
| + | NET: Registered protocol family 17 | ||
| + | Ebtables v2.0 registered | ||
| + | 8021q: 802.1Q VLAN Support v1.8 | ||
| + | Boot from / | ||
| + | VFS: Mounted root (squashfs filesystem) readonly on device 31:7. | ||
| + | devtmpfs: mounted | ||
| + | Freeing unused kernel memory: 232K (81666000 - 816a0000) | ||
| + | Arcadyan the primary config checkout succeed. | ||
| + | Arcadyan the second config checkout succeed. | ||
| + | arca.dbus.mng: | ||
| + | agent_handler(236): | ||
| + | MD5=[2e9a0e55bd3587fc2d845b190837c07b] | ||
| + | |||
| + | Please press Enter to activate this console. | ||
| + | Raeth v3.1 (Tasklet) | ||
| + | set CLK_CFG_0 = 0x40a00020!!!!!!!!!!!!!!!!!!1 | ||
| + | phy_free_head is 0xc18000!!! | ||
| + | phy_free_tail_phy is 0xc19ff0!!! | ||
| + | txd_pool=a0c60000 phy_txd_pool=00C60000 | ||
| + | ei_local-> | ||
| + | free_txd: 00c60010, ei_local-> | ||
| + | | ||
| + | ----------------+---------+-------- | ||
| + | | ||
| + | |||
| + | phy_qrx_ring = 0x00c1a000, qrx_ring = 0xa0c1a000 | ||
| + | |||
| + | phy_rx_ring0 = 0x00c1c000, rx_ring[0] = 0xa0c1c000 | ||
| + | MT7530 Reset Completed!! | ||
| + | change HW-TRAP to 0x17c8f | ||
| + | set LAN/WAN LLLLW | ||
| + | GMAC1_MAC_ADRH -- : 0x0000000c | ||
| + | GMAC1_MAC_ADRL -- : 0x432880ab | ||
| + | GDMA2_MAC_ADRH -- : 0x0000000c | ||
| + | GDMA2_MAC_ADRL -- : 0x432880ac | ||
| + | eth3: ===> VirtualIF_open | ||
| + | MT7621 GE2 link rate to 1G | ||
| + | CDMA_CSG_CFG = 81000000 | ||
| + | GDMA1_FWD_CFG = 20710000 | ||
| + | GDMA2_FWD_CFG = 20710000 | ||
| + | device eth2 entered promiscuous mode | ||
| + | br0: port 1(eth2) entered forwarding state | ||
| + | br0: port 1(eth2) entered forwarding state | ||
| + | device eth2.1000 entered promiscuous mode | ||
| + | br1: port 1(eth2.1000) entered forwarding state | ||
| + | br1: port 1(eth2.1000) entered forwarding state | ||
| + | DriverOwn():: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | ==> UserCfgInit: | ||
| + | [wifi_fwd_set_cb_num] band_cb_offset=33, | ||
| + | multi-profile merge success, en: | ||
| + | MacAddress1 = 00: | ||
| + | RT_CfgSetMacAddress : invalid length (0) | ||
| + | RT_CfgSetMacAddress : invalid length (0) | ||
| + | E2pAccessMode=2 | ||
| + | SSID[0]=my-ssid, | ||
| + | SSID[1]=my-ssid, | ||
| + | SSID[2]=KPN Fon, EdcaIdx=0 | ||
| + | SSID[3]=KPN_Guest, | ||
| + | RTMPSetProfileParameters(): | ||
| + | TriBandChGrp=0/ | ||
| + | cfg_mode=15 | ||
| + | cfg_mode=15 | ||
| + | wmode_band_equal(): | ||
| + | cfg_mode=6 | ||
| + | cfg_mode=6 | ||
| + | cfg_mode=6 | ||
| + | cfg_mode=6 | ||
| + | cfg_mode=6 | ||
| + | cfg_mode=6 | ||
| + | BandSteering=1 | ||
| + | BndStrgBssIdx=1; | ||
| + | [TxPower] BAND0: 30, BAND1: 30 | ||
| + | [SKUenable] BAND0: 1, BAND1: 1 | ||
| + | [PERCENTAGEenable] BAND0: 1, BAND1: 1 | ||
| + | [BFBACKOFFenable] BAND0: 0, BAND1: 0 | ||
| + | CalCacheApply = 0 | ||
| + | APEdca0 | ||
| + | Valid=1 | ||
| + | APAifsn[0]=3 | ||
| + | APAifsn[1]=7 | ||
| + | APAifsn[2]=1 | ||
| + | APAifsn[3]=1 | ||
| + | APEdca1 | ||
| + | Valid=1 | ||
| + | APAifsn[0]=3 | ||
| + | APAifsn[1]=7 | ||
| + | APAifsn[2]=1 | ||
| + | APAifsn[3]=1 | ||
| + | APEdca2 | ||
| + | APEdca3 | ||
| + | BSSAifsn[0]=3 | ||
| + | BSSAifsn[1]=7 | ||
| + | BSSAifsn[2]=2 | ||
| + | BSSAifsn[3]=2 | ||
| + | BSSAifsn[0]=3 | ||
| + | BSSAifsn[1]=7 | ||
| + | BSSAifsn[2]=2 | ||
| + | BSSAifsn[3]=2 | ||
| + | BSSAifsn[0]=3 | ||
| + | BSSAifsn[1]=7 | ||
| + | BSSAifsn[2]=2 | ||
| + | BSSAifsn[3]=2 | ||
| + | BSSAifsn[0]=3 | ||
| + | BSSAifsn[1]=7 | ||
| + | BSSAifsn[2]=2 | ||
| + | BSSAifsn[3]=2 | ||
| + | APSDCapable[0]=0 | ||
| + | APSDCapable[1]=0 | ||
| + | default ApCliAPSDCapable[0]=0 | ||
| + | default ApCliAPSDCapable[1]=0 | ||
| + | DfsZeroWaitCacTime=255/ | ||
| + | RTMPSetProfileParameters(): | ||
| + | RTMPSetProfileParameters(): | ||
| + | [PMF]Set_PMFMFPC_Proc:: | ||
| + | [PMF]Set_PMFMFPC_Proc:: | ||
| + | [PMF]Set_PMFMFPR_Proc:: | ||
| + | [PMF]Set_PMFMFPR_Proc:: | ||
| + | [PMF]Set_PMFSHA256_Proc:: | ||
| + | [PMF]Set_PMFSHA256_Proc:: | ||
| + | cfg_mode=8 | ||
| + | cfg_mode=9 | ||
| + | AndesSendCmdMsg: | ||
| + | HT: WDEV[0] Ext Channel = BELOW | ||
| + | HT: WDEV[1] Ext Channel = BELOW | ||
| + | HT: WDEV[2] Ext Channel = BELOW | ||
| + | HT: WDEV[3] Ext Channel = BELOW | ||
| + | HT: greenap_cap = 0 | ||
| + | IcapMode = 0 | ||
| + | WtcSetMaxStaNum: | ||
| + | Top Init Done! | ||
| + | Use alloc_skb | ||
| + | RX[0] DESC a0c14000 size = 16384 | ||
| + | RX[1] DESC a0c12000 size = 8192 | ||
| + | Hif Init Done! | ||
| + | ctl->txq = c0519d90 | ||
| + | ctl->rxq = c0519d9c | ||
| + | ctl-> | ||
| + | ctl-> | ||
| + | ctl-> | ||
| + | ctl-> | ||
| + | mt7615_fw_prepare(): | ||
| + | mt7615_fw_prepare(2687): | ||
| + | AndesMTLoadRomMethodFwDlRing(1035), | ||
| + | AndesRestartCheck: | ||
| + | AndesRestartCheck: | ||
| + | 20170809192718a | ||
| + | |||
| + | platform = | ||
| + | ALPS | ||
| + | hw/sw version = | ||
| + | 8a108a10 | ||
| + | patch version = | ||
| + | 00000010 | ||
| + | Patch SEM Status=2 | ||
| + | MtCmdPatchSemGet: | ||
| + | |||
| + | Patch is not ready && get semaphore success, SemStatus(2) | ||
| + | EventGenericEventHandler: | ||
| + | MtCmdAddressLenReq: | ||
| + | MtCmdPatchFinishReq | ||
| + | EventGenericEventHandler: | ||
| + | Send checksum req.. | ||
| + | Patch SEM Status=3 | ||
| + | MtCmdPatchSemGet: | ||
| + | |||
| + | Release patch semaphore, SemStatus(3) | ||
| + | AndesMTEraseRomPatch | ||
| + | WfMcuHwInit: | ||
| + | AndesMTLoadFwMethodFwDlRing(809), | ||
| + | Build Date: | ||
| + | Build Date: | ||
| + | AndesRestartCheck: | ||
| + | AndesRestartCheck: | ||
| + | EventGenericEventHandler: | ||
| + | MtCmdAddressLenReq: | ||
| + | EventGenericEventHandler: | ||
| + | MtCmdAddressLenReq: | ||
| + | MtCmdFwStartReq: | ||
| + | EventGenericEventHandler: | ||
| + | Build Date: | ||
| + | EventGenericEventHandler: | ||
| + | MtCmdAddressLenReq: | ||
| + | MtCmdFwStartReq: | ||
| + | EventGenericEventHandler: | ||
| + | WfMcuHwInit: | ||
| + | MCU Init Done! | ||
| + | e[41m MtCmdSetRlmPorCal: | ||
| + | efuse_probe: | ||
| + | RtmpChipOpsEepromHook:: | ||
| + | RtmpEepromGetDefault:: | ||
| + | RtmpChipOpsEepromHook: | ||
| + | NVM is FLASH mode. dev_idx [0] FLASH OFFSET [0x0] | ||
| + | e[34mNICReadEEPROMParameters: | ||
| + | e[34mNICReadEEPROMParameters: | ||
| + | Country Region from e2p = 101 | ||
| + | mt7615_antenna_default_reset(): | ||
| + | mt7615_antenna_default_reset(): | ||
| + | mt7615_antenna_default_reset(): | ||
| + | rtmp_read_txpwr_from_eeprom(233): | ||
| + | RTMPReadTxPwrPerRate(1381): | ||
| + | RcRadioInit(): | ||
| + | RcRadioInit(): | ||
| + | RcRadioInit(): | ||
| + | MtCmdSetDbdcCtrl: | ||
| + | Band Rf: 1, Phy Mode: 2 | ||
| + | Band Rf: 2, Phy Mode: 1 | ||
| + | AntCfgInit(2807): | ||
| + | MtSingleSkuLoadParam: | ||
| + | MtBfBackOffLoadTable: | ||
| + | EEPROM Init Done! | ||
| + | mt_mac_init()--> | ||
| + | mt_mac_pse_init(2750): | ||
| + | mt7615_init_mac_cr()--> | ||
| + | mt7615_init_mac_cr(): | ||
| + | mt7615_init_mac_cr(): | ||
| + | MtAsicSetMacMaxLen(1300): | ||
| + | < | ||
| + | CmdRxHdrTransBLUpdateRsp:: | ||
| + | CmdRxHdrTransBLUpdateRsp:: | ||
| + | CmdRxHdrTransBLUpdateRsp:: | ||
| + | MAC Init Done! | ||
| + | MT7615BBPInit(): | ||
| + | Band 0: valid=1, isDBDC=0, Band=2, CBW=1, CentCh/ | ||
| + | Band 1: valid=0, isDBDC=0, Band=0, CBW=0, CentCh/ | ||
| + | MT7615BBPInit() todo | ||
| + | PHY Init Done! | ||
| + | tx_pwr_comp_init(): | ||
| + | MtCmdSetMacTxRx: | ||
| + | MtCmdSetMacTxRx: | ||
| + | CountryCode(2.4G/ | ||
| + | WifiSysOpen(), | ||
| + | wdev_attr_update(): | ||
| + | MtCmdSetDbdcCtrl: | ||
| + | radio_operate_init : Error! Check! wdev-> | ||
| + | ApAutoChannelAtBootUp-----------------> | ||
| + | ApAutoChannelAtBootUp: | ||
| + | ApAutoChannelAtBootUp< | ||
| + | WifiSysClose(), | ||
| + | WifiSysOpen(), | ||
| + | wdev_attr_update(): | ||
| + | MtCmdSetDbdcCtrl: | ||
| + | radio_operate_init : Error! Check! wdev-> | ||
| + | MtAsicSetChBusyStat(840): | ||
| + | [PMF]APPMFInit:: | ||
| + | [PMF]WPAMakeRsnIeCap: | ||
| + | HcUpdatePhyMode(): | ||
| + | CountryCode(2.4G/ | ||
| + | Enable 20/40 BSSCoex Channel Scan(BssCoex=1) | ||
| + | wtc_acquire_groupkey_wcid: | ||
| + | | ||
| + | bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO), | ||
| + | MtCmdSetDbdcCtrl: | ||
| + | e[1;33m [RadarStateCheck]Set into RD_NORMAL_MODE e[m | ||
| + | MtCmdTxPowerSKUCtrl: | ||
| + | MtCmdTxPowerPercentCtrl: | ||
| + | MtCmdTxBfBackoffCtrl: | ||
| + | mt7615_bbp_adjust(): | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 1 is 0, do runtime cal , skip RX reload | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 0 is 0, do runtime cal , skip TX reload | ||
| + | MtCmdChannelSwitch: | ||
| + | BW = 2,TXStream = 2, RXStream = 2, scan(0) | ||
| + | ap_phy_rrm_init_byRf(): | ||
| + | [WrapDfsRadarDetectStart]: | ||
| + | [WrapDfsRadarDetectStart]: | ||
| + | LeadTimeForBcn, | ||
| + | MtAsicSetRalinkBurstMode(2605): | ||
| + | MtAsicSetPiggyBack(777): | ||
| + | MtAsicSetTxPreamble(2584): | ||
| + | RTMPSetLEDStatus: | ||
| + | AndesLedEnhanceOP: | ||
| + | WifiFwdSet:: | ||
| + | ap_ftkd> Initialize FT KDP Module... | ||
| + | e[1; | ||
| + | e[0mMain bssid = re: | ||
| + | AsicRadioOnOffCtrl(): | ||
| + | MtCmdSetMacTxRx: | ||
| + | MtCmdSetMacTxRx: | ||
| + | MCS Set = ff ff 00 00 01 | ||
| + | <==== mt_wifi_init, | ||
| + | MtCmdEDCCACtrl: | ||
| + | MtCmdEDCCACtrl: | ||
| + | WtcSetMaxStaNum: | ||
| + | red_is_enabled: | ||
| + | cp_support_is_enabled: | ||
| + | e[1; | ||
| + | e[0mCorrect apidx from 1 to 0 for WscUUIDInit | ||
| + | Generate UUID for apidx(0) | ||
| + | device ra0 entered promiscuous mode | ||
| + | br0: port 2(ra0) entered forwarding state | ||
| + | br0: port 2(ra0) entered forwarding state | ||
| + | WifiSysOpen(), | ||
| + | wdev_attr_update(): | ||
| + | MtCmdSetDbdcCtrl: | ||
| + | [PMF]APPMFInit:: | ||
| + | [PMF]WPAMakeRsnIeCap: | ||
| + | HcUpdatePhyMode(): | ||
| + | CountryCode(2.4G/ | ||
| + | Enable 20/40 BSSCoex Channel Scan(BssCoex=1) | ||
| + | MtCmdSetMacTxRx: | ||
| + | MtCmdSetMacTxRx: | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 1 is 0, do runtime cal , skip RX reload | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 0 is 0, do runtime cal , skip TX reload | ||
| + | MtCmdChannelSwitch: | ||
| + | BW = 0,TXStream = 2, RXStream = 2, scan(1) | ||
| + | AP OBSS SYNC - BBP R4 to 20MHz.l | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 1 is 0, do runtime cal , skip RX reload | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 0 is 0, do runtime cal , skip TX reload | ||
| + | MtCmdChannelSwitch: | ||
| + | BW = 0,TXStream = 2, RXStream = 2, scan(1) | ||
| + | AP OBSS SYNC - BBP R4 to 20MHz.l | ||
| + | : | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 1 is 0, do runtime cal , skip RX reload | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 0 is 0, do runtime cal , skip TX reload | ||
| + | MtCmdChannelSwitch: | ||
| + | BW = 0,TXStream = 2, RXStream = 2, scan(1) | ||
| + | AP OBSS SYNC - BBP R4 to 20MHz.l | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 1 is 0, do runtime cal , skip RX reload | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 0 is 0, do runtime cal , skip TX reload | ||
| + | MtCmdChannelSwitch: | ||
| + | BW = 0,TXStream = 2, RXStream = 2, scan(1) | ||
| + | AP OBSS SYNC - BBP R4 to 20MHz.l | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 1 is 0, do runtime cal , skip RX reload | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 0 is 0, do runtime cal , skip TX reload | ||
| + | MtCmdChannelSwitch: | ||
| + | BW = 0,TXStream = 2, RXStream = 2, scan(1) | ||
| + | AP OBSS SYNC - BBP R4 to 20MHz.l | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 1 is 0, do runtime cal , skip RX reload | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 0 is 0, do runtime cal , skip TX reload | ||
| + | MtCmdChannelSwitch: | ||
| + | BW = 0,TXStream = 2, RXStream = 2, scan(1) | ||
| + | AP OBSS SYNC - BBP R4 to 20MHz.l | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 1 is 0, do runtime cal , skip RX reload | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 0 is 0, do runtime cal , skip TX reload | ||
| + | MtCmdChannelSwitch: | ||
| + | BW = 0,TXStream = 2, RXStream = 2, scan(1) | ||
| + | AP OBSS SYNC - BBP R4 to 20MHz.l | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 1 is 0, do runtime cal , skip RX reload | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 0 is 0, do runtime cal , skip TX reload | ||
| + | MtCmdChannelSwitch: | ||
| + | BW = 0,TXStream = 2, RXStream = 2, scan(1) | ||
| + | AP OBSS SYNC - BBP R4 to 20MHz.l | ||
| + | wtc_acquire_groupkey_wcid: | ||
| + | | ||
| + | bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO), | ||
| + | MtCmdSetDbdcCtrl: | ||
| + | e[1;33m [RadarStateCheck]Set into RD_NORMAL_MODE e[m | ||
| + | MtCmdTxPowerSKUCtrl: | ||
| + | MtCmdTxPowerPercentCtrl: | ||
| + | MtCmdTxBfBackoffCtrl: | ||
| + | mt7615_bbp_adjust(): | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 1 is 0, do runtime cal , skip RX reload | ||
| + | mt7615_apply_cal_data() : eeprom 0x52 bit 0 is 0, do runtime cal , skip TX reload | ||
| + | MtCmdChannelSwitch: | ||
| + | BW = 0,TXStream = 2, RXStream = 2, scan(0) | ||
| + | ap_phy_rrm_init_byRf(): | ||
| + | e[1; | ||
| + | e[0mLeadTimeForBcn, | ||
| + | Generate UUID for apidx(1) | ||
| + | device rax0 entered promiscuous mode | ||
| + | br0: port 3(rax0) entered forwarding state | ||
| + | br0: port 3(rax0) entered forwarding state | ||
| + | ==> WscBuildProbeRespIE: | ||
| + | ==> Set_AP_WscConfStatus_Proc: | ||
| + | ==> WscBuildProbeRespIE: | ||
| + | [00: | ||
| + | [00: | ||
| + | [00: | ||
| + | [00: | ||
| + | e[0mstart syslog-ng... | ||
| + | Port[0]: up => down! | ||
| + | Port[1]: up => down! | ||
| + | WAN: Up => Down | ||
| + | start_upnp: wan_idx -1 | ||
| + | Call Update Tr69 Rule. | ||
| + | [00: | ||
| + | BndStrg_InfStatusRsp: | ||
| + | rg_periodic_exec | ||
| + | BndStrg_InfStatusRsp: | ||
| + | ]e[1; | ||
| + | e[0m[00: | ||
| + | [00: | ||
| + | [bndstrg_inf_status_polling]inf_name: | ||
| + | [00: | ||
| + | [bndstrg_inf_status_polling]inf_name: | ||
| + | [00: | ||
| + | [00: | ||
| + | [00: | ||
| + | rg_periodic_execSend DISASSOC frame(3) with ra1 | ||
| + | ]e[1; | ||
| + | > | ||
| + | BL_EN | ||
| + | e[0m[00: | ||
| + | [00: | ||
| + | [00: | ||
| + | e[0mTime out! You may increase DEFAULT_TIMEOUT_COUNT[10]! | ||
| + | </ | ||
| </ | </ | ||
| ==== OpenWrt bootlog ==== | ==== OpenWrt bootlog ==== | ||
| <WRAP bootlog> | <WRAP bootlog> | ||
| - | < | + | < |
| + | =================================================================== | ||
| + | | ||
| + | | ||
| + | ================================================================== | ||
| + | Change MPLL source from XTAL to CR... | ||
| + | do MEMPLL setting.. | ||
| + | MEMPLL Config : 0x11100000 | ||
| + | 3PLL mode + External loopback | ||
| + | === XTAL-40Mhz === DDR-1200Mhz === | ||
| + | PLL4 FB_DL: 0x3, 1/0 = 571/453 0D000000 | ||
| + | PLL3 FB_DL: 0x11, 1/0 = 600/424 45000000 | ||
| + | PLL2 FB_DL: 0x15, 1/0 = 611/413 55000000 | ||
| + | do DDR setting..[01F40000] | ||
| + | Apply DDR3 Setting...(use customer AC) | ||
| + | 0 8 | ||
| + | -------------------------------------------------------------------------------- | ||
| + | 0000: | ||
| + | 0001: | ||
| + | 0002: | ||
| + | 0003: | ||
| + | 0004: | ||
| + | 0005: | ||
| + | 0006: | ||
| + | 0007: | ||
| + | 0008: | ||
| + | 0009: | ||
| + | 000A: | ||
| + | 000B: | ||
| + | 000C: | ||
| + | 000D: | ||
| + | 000E: | ||
| + | 000F: | ||
| + | 0010: | ||
| + | 0011: | ||
| + | 0012: | ||
| + | 0013: | ||
| + | 0014: | ||
| + | 0015: | ||
| + | 0016: | ||
| + | 0017: | ||
| + | 0018: | ||
| + | 0019: | ||
| + | 001A: | ||
| + | 001B: | ||
| + | 001C: | ||
| + | 001D: | ||
| + | 001E: | ||
| + | 001F: | ||
| + | rank 0 coarse = 15 | ||
| + | rank 0 fine = 72 | ||
| + | B:| 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 | ||
| + | opt_dle value:11 | ||
| + | DRAMC_R0DELDLY[018]=00001F1F | ||
| + | ================================================================== | ||
| + | RX DQS perbit delay software calibration | ||
| + | ================================================================== | ||
| + | 1.0-15 bit dq delay value | ||
| + | ================================================================== | ||
| + | bit| | ||
| + | -------------------------------------- | ||
| + | 0 | 9 7 8 10 7 8 8 7 8 8 | ||
| + | 10 | 9 10 9 12 9 10 | ||
| + | -------------------------------------- | ||
| + | |||
| + | ================================================================== | ||
| + | 2.dqs window | ||
| + | x=pass dqs delay value (min~max)center | ||
| + | y=0-7bit DQ of every group | ||
| + | input delay:DQS0 =31 DQS1 = 31 | ||
| + | ================================================================== | ||
| + | bit DQS0 bit | ||
| + | 0 (1~58)29 | ||
| + | 1 (1~58)29 | ||
| + | 2 (1~59)30 | ||
| + | 3 (1~60)30 | ||
| + | 4 (1~59)30 | ||
| + | 5 (1~60)30 | ||
| + | 6 (1~60)30 | ||
| + | 7 (1~61)31 | ||
| + | ================================================================== | ||
| + | 3.dq delay value last | ||
| + | ================================================================== | ||
| + | bit| 0 1 2 3 4 5 6 7 8 9 | ||
| + | -------------------------------------- | ||
| + | 0 | 11 9 9 11 8 9 9 7 10 10 | ||
| + | 10 | 10 12 10 13 9 11 | ||
| + | ================================================================== | ||
| + | ================================================================== | ||
| + | | ||
| + | ================================================================== | ||
| + | DQS loop = 15, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[0]=15, | ||
| + | dqs_perbyte_dly.last_dqsdly_pass[1]=15, | ||
| + | DQ loop=15, cmp_err_1 = ffff00aa | ||
| + | dqs_perbyte_dly.last_dqdly_pass[1]=15, | ||
| + | DQ loop=14, cmp_err_1 = ffff00a0 | ||
| + | DQ loop=13, cmp_err_1 = ffff0080 | ||
| + | DQ loop=12, cmp_err_1 = ffff0000 | ||
| + | dqs_perbyte_dly.last_dqdly_pass[0]=12, | ||
| + | byte:0, (DQS, | ||
| + | byte:1, (DQS, | ||
| + | 20, | ||
| + | [EMI] DRAMC calibration passed | ||
| + | |||
| + | =================================================================== | ||
| + | | ||
| + | | ||
| + | =================================================================== | ||
| + | |||
| + | |||
| + | U-Boot 1.1.3 (Dec 4 2017 - 11:37:57) 0.00 | ||
| + | |||
| + | Board: Ralink APSoC DRAM: 128 MB | ||
| + | relocate_code Pointer at: 87f94000 | ||
| + | |||
| + | Config XHCI 40M PLL | ||
| + | ****************************** | ||
| + | Software System Reset Occurred | ||
| + | ****************************** | ||
| + | flash manufacture id: c2, device id 20 19 | ||
| + | find flash: MX25L25635E | ||
| + | ============================================ | ||
| + | Ralink UBoot Version: 5.0.0.1 | ||
| + | -------------------------------------------- | ||
| + | ASIC MT7621A DualCore (MAC to MT7530 Mode) | ||
| + | DRAM_CONF_FROM: | ||
| + | DRAM_TYPE: DDR3 | ||
| + | DRAM bus: 16 bit | ||
| + | Xtal Mode=3 OCP Ratio=1/3 | ||
| + | Flash component: 32 MBytes NOR Flash | ||
| + | Date: | ||
| + | ============================================ | ||
| + | icache: sets:256, ways:4, linesz:32 , | ||
| + | dcache: sets:256, ways:4, linesz:32 , | ||
| + | |||
| + | ##### The CPU freq = 880 MHZ #### | ||
| + | | ||
| + | # | ||
| + | set LAN/WAN LLLLW | ||
| + | |||
| + | Please choose the operation: | ||
| + | 1: Load system code to SDRAM via TFTP. | ||
| + | 2: Load system code then write to Flash via TFTP. | ||
| + | 3: Boot system code via Flash (default). | ||
| + | 4: Entr boot command line interface. | ||
| + | 7: Load Boot Loader code then write to Flash via Serial. | ||
| + | 9: Load Boot Loader code then write to Flash via TFTP. | ||
| + | default: 3 0 | ||
| + | |||
| + | 3: System Boot system code via Flash[0]. | ||
| + | ## Booting image at bc050000 ... | ||
| + | old glbcfg partition is broken, magic=[0x23494255][0x55424923]! | ||
| + | | ||
| + | Image Name: MIPS OpenWrt Linux-5.10.161 | ||
| + | Image Type: MIPS Linux Kernel Image (uncompressed) | ||
| + | Data Size: 2692535 Bytes = 2.6 MB | ||
| + | Load Address: 80001000 | ||
| + | Entry Point: | ||
| + | | ||
| + | OK | ||
| + | No initrd | ||
| + | ## Transferring control to Linux (at address 80001000) ... | ||
| + | ## Giving linux memsize in MB, 128 | ||
| + | |||
| + | Starting kernel ... | ||
| + | |||
| + | |||
| + | |||
| + | OpenWrt kernel loader for MIPS based SoC | ||
| + | Copyright (C) 2011 Gabor Juhos < | ||
| + | Decompressing kernel... done! | ||
| + | Starting kernel at 80001000... | ||
| + | |||
| + | [ 0.000000] Linux version 5.10.161 (builder@buildhost) (mipsel-openwrt-linux-musl-gcc (OpenWrt GCC 11.3.0 r21603+2-fb15cb4ce9) 11.3.0, GNU ld (GNU Binutils) 2.37) #0 SMP Tue Dec 27 14:26:24 2022 | ||
| + | [ 0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3 | ||
| + | [ 0.000000] printk: bootconsole [early0] enabled | ||
| + | [ 0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.000000] MIPS: machine is Arcadyan WE420223-99 | ||
| + | [ 0.000000] Initrd not found or empty - disabling initrd | ||
| + | [ 0.000000] VPE topology {2,2} total 4 | ||
| + | [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.000000] Zone ranges: | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] Movable zone start for each node | ||
| + | [ 0.000000] Early memory node ranges | ||
| + | [ 0.000000] | ||
| + | [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff] | ||
| + | [ 0.000000] percpu: Embedded 15 pages/cpu s30480 r8192 d22768 u61440 | ||
| + | [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 32480 | ||
| + | [ 0.000000] Kernel command line: console=ttyS0, | ||
| + | [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear) | ||
| + | [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear) | ||
| + | [ 0.000000] Writing ErrCtl register=00000000 | ||
| + | [ 0.000000] Readback ErrCtl register=00000000 | ||
| + | [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off | ||
| + | [ 0.000000] Memory: 119472K/ | ||
| + | [ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, | ||
| + | [ 0.000000] rcu: Hierarchical RCU implementation. | ||
| + | [ 0.000000] Tracing variant of Tasks RCU enabled. | ||
| + | [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. | ||
| + | [ 0.000000] NR_IRQS: 256 | ||
| + | [ 0.000000] CPU Clock: 880MHz | ||
| + | [ 0.000000] clocksource: | ||
| + | [ 0.000013] sched_clock: | ||
| + | [ 0.015854] clocksource: | ||
| + | [ 0.033809] Calibrating delay loop... 586.13 BogoMIPS (lpj=2930688) | ||
| + | [ 0.106131] pid_max: default: 32768 minimum: 301 | ||
| + | [ 0.115443] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) | ||
| + | [ 0.129849] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) | ||
| + | [ 0.148140] rcu: Hierarchical SRCU implementation. | ||
| + | [ 0.157952] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build | ||
| + | [ 0.173529] smp: Bringing up secondary CPUs ... | ||
| + | [ 0.183279] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.183290] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.183301] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.183376] CPU1 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.243361] Synchronize counters for CPU 1: done. | ||
| + | [ 0.305528] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.305537] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.305545] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.305593] CPU2 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.364493] Synchronize counters for CPU 2: done. | ||
| + | [ 0.424841] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. | ||
| + | [ 0.424850] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | ||
| + | [ 0.424858] MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | ||
| + | [ 0.424912] CPU3 revision is: 0001992f (MIPS 1004Kc) | ||
| + | [ 0.484074] Synchronize counters for CPU 3: done. | ||
| + | [ 0.543685] smp: Brought up 1 node, 4 CPUs | ||
| + | [ 0.556200] clocksource: | ||
| + | [ 0.575716] futex hash table entries: 1024 (order: 3, 32768 bytes, linear) | ||
| + | [ 0.589534] pinctrl core: initialized pinctrl subsystem | ||
| + | [ 0.602231] NET: Registered protocol family 16 | ||
| + | [ 0.612267] thermal_sys: | ||
| + | [ 0.613296] cpuidle: using governor teo | ||
| + | [ 0.638657] rt2880-pinmux pinctrl: there is not valid maps for state default | ||
| + | [ 0.683299] clocksource: | ||
| + | [ 0.695156] NET: Registered protocol family 2 | ||
| + | [ 0.704010] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear) | ||
| + | [ 0.719695] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear) | ||
| + | [ 0.736368] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear) | ||
| + | [ 0.751484] TCP bind hash table entries: 1024 (order: 1, 8192 bytes, linear) | ||
| + | [ 0.765484] TCP: Hash tables configured (established 1024 bind 1024) | ||
| + | [ 0.778246] UDP hash table entries: 256 (order: 1, 8192 bytes, linear) | ||
| + | [ 0.791129] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear) | ||
| + | [ 0.805229] NET: Registered protocol family 1 | ||
| + | [ 0.813806] PCI: CLS 0 bytes, default 32 | ||
| + | [ 0.823874] workingset: timestamp_bits=14 max_order=15 bucket_order=1 | ||
| + | [ 0.841029] squashfs: version 4.0 (2009/ | ||
| + | [ 0.852578] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc. | ||
| + | [ 0.873035] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251) | ||
| + | [ 0.889474] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.900824] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.912094] mt7621_gpio 1e000600.gpio: | ||
| + | [ 0.923818] Serial: 8250/16550 driver, 16 ports, IRQ sharing enabled | ||
| + | [ 0.940573] printk: console [ttyS0] disabled | ||
| + | [ 0.949067] 1e000c00.uartlite: | ||
| + | [ 0.966996] printk: console [ttyS0] enabled | ||
| + | [ 0.966996] printk: console [ttyS0] enabled | ||
| + | [ 0.983535] printk: bootconsole [early0] disabled | ||
| + | [ 0.983535] printk: bootconsole [early0] disabled | ||
| + | [ 1.005547] spi-mt7621 1e000b00.spi: | ||
| + | [ 1.017892] spi-nor spi0.0: mx25l25635e (32768 Kbytes) | ||
| + | [ 1.028295] 12 fixed-partitions partitions found on MTD device spi0.0 | ||
| + | [ 1.041148] Creating 12 MTD partitions on " | ||
| + | [ 1.050884] 0x000000000000-0x000002000000 : " | ||
| + | [ 1.061216] 0x000000000000-0x000000030000 : " | ||
| + | [ 1.072829] 0x000000030000-0x000000040000 : " | ||
| + | [ 1.083807] 0x000000040000-0x000000050000 : " | ||
| + | [ 1.094885] 0x000000050000-0x000001fb0000 : " | ||
| + | [ 1.105803] 0x000000490000-0x000001fb0000 : " | ||
| + | [ 1.116620] mtd: setting mtd5 (rootfs) as root device | ||
| + | [ 1.126800] mtdsplit: no squashfs found in " | ||
| + | [ 1.136564] 0x000001000000-0x000001fb0000 : " | ||
| + | [ 1.147590] 0x000001440000-0x000001fb0000 : " | ||
| + | [ 1.158715] 0x000001fb0000-0x000001fc0000 : " | ||
| + | [ 1.169716] 0x000001fc0000-0x000001fd0000 : " | ||
| + | [ 1.181486] 0x000001fd0000-0x000001fe0000 : " | ||
| + | [ 1.192745] 0x000001fe0000-0x000001ff0000 : " | ||
| + | [ 1.254756] mt7530 mdio-bus: | ||
| + | [ 1.270802] mtk_soc_eth 1e100000.ethernet: | ||
| + | [ 1.287960] mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 20 | ||
| + | [ 1.304794] mtk_soc_eth 1e100000.ethernet: | ||
| + | [ 1.321891] mtk_soc_eth 1e100000.ethernet swp0: mediatek frame engine at 0xbe100000, irq 20 | ||
| + | [ 1.339883] i2c /dev entries driver | ||
| + | [ 1.349384] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.362784] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.380312] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.396622] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.413013] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.425752] NET: Registered protocol family 10 | ||
| + | [ 1.436434] Segment Routing with IPv6 | ||
| + | [ 1.443902] NET: Registered protocol family 17 | ||
| + | [ 1.452830] bridge: filtering via arp/ | ||
| + | [ 1.479010] 8021q: 802.1Q VLAN Support v1.8 | ||
| + | [ 1.490791] mt7530 mdio-bus: | ||
| + | [ 1.523677] mt7530 mdio-bus:1f swp1 (uninitialized): | ||
| + | [ 1.547639] mt7530 mdio-bus: | ||
| + | [ 1.564450] DSA: tree 0 setup | ||
| + | [ 1.570659] rt2880-pinmux pinctrl: pcie is already enabled | ||
| + | [ 1.581673] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.595051] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.612586] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.628889] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.645286] mt7621-pci-phy 1e149000.pcie-phy: | ||
| + | [ 1.660381] mt7621-pci-phy 1e14a000.pcie-phy: | ||
| + | [ 1.675378] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.790050] mt7621-pci-phy 1e149000.pcie-phy: | ||
| + | [ 1.801174] mt7621-pci-phy 1e14a000.pcie-phy: | ||
| + | [ 1.912472] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.926353] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.940216] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.949936] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.968667] mt7621-pci 1e140000.pcie: | ||
| + | [ 1.981341] pci_bus 0000:00: root bus resource [io 0x1e160000-0x1e16ffff] | ||
| + | [ 1.995051] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] | ||
| + | [ 2.008749] pci_bus 0000:00: root bus resource [bus 00-ff] | ||
| + | [ 2.019677] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff]) | ||
| + | [ 2.039991] pci 0000: | ||
| + | [ 2.051976] pci 0000: | ||
| + | [ 2.064478] pci 0000: | ||
| + | [ 2.077024] pci 0000: | ||
| + | [ 2.085019] pci 0000: | ||
| + | [ 2.098149] pci 0000: | ||
| + | [ 2.110179] pci 0000: | ||
| + | [ 2.124240] pci 0000: | ||
| + | [ 2.136901] pci 0000: | ||
| + | [ 2.167861] pci 0000: | ||
| + | [ 2.178292] pci 0000: | ||
| + | [ 2.190442] pci 0000: | ||
| + | [ 2.203976] pci 0000: | ||
| + | [ 2.218363] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 | ||
| + | [ 2.231590] pci 0000: | ||
| + | [ 2.244779] pci 0000: | ||
| + | [ 2.258646] pci 0000: | ||
| + | [ 2.272171] pci 0000: | ||
| + | [ 2.286563] pci 0000: | ||
| + | [ 2.300089] pci 0000: | ||
| + | [ 2.313628] pci 0000: | ||
| + | [ 2.328202] pci 0000: | ||
| + | [ 2.338092] pci 0000: | ||
| + | [ 2.351614] pci 0000: | ||
| + | [ 2.365140] pci 0000: | ||
| + | [ 2.380951] ubi0: attaching mtd5 | ||
| + | [ 2.393603] mt7530 mdio-bus: | ||
| + | [ 2.433220] ubi0: scanning is finished | ||
| + | [ 2.453234] ubi0: attached mtd5 (name " | ||
| + | [ 2.464596] ubi0: PEB size: 65536 bytes (64 KiB), LEB size: 65408 bytes | ||
| + | [ 2.477780] ubi0: min./max. I/O unit sizes: 1/256, sub-page size 1 | ||
| + | [ 2.490082] ubi0: VID header offset: 64 (aligned 64), data offset: 128 | ||
| + | [ 2.503076] ubi0: good PEBs: 434, bad PEBs: 0, corrupted PEBs: 0 | ||
| + | [ 2.515036] ubi0: user volume: 2, internal volumes: 1, max. volumes count: 128 | ||
| + | [ 2.529420] ubi0: max/mean erase counter: 9/5, WL threshold: 4096, image sequence number: 1657914794 | ||
| + | [ 2.547599] ubi0: available PEBs: 0, total reserved PEBs: 434, PEBs reserved for bad PEB handling: 0 | ||
| + | [ 2.565816] ubi0: background thread " | ||
| + | [ 2.565936] UBI: block: volume size is not a multiple of 512, last 256 bytes are ignored! | ||
| + | [ 2.595279] block ubiblock0_0: | ||
| + | [ 2.614412] VFS: Mounted root (squashfs filesystem) readonly on device 254:0. | ||
| + | [ 2.632831] Freeing unused kernel memory: 1292K | ||
| + | [ 2.641888] This architecture does not have kernel memory protection. | ||
| + | [ 2.654743] Run /sbin/init as init process | ||
| + | [ 3.204027] init: Console is alive | ||
| + | [ 3.211196] init: - watchdog - | ||
| + | [ 4.225372] kmodloader: loading kernel modules from / | ||
| + | [ 4.347999] usbcore: registered new interface driver usbfs | ||
| + | [ 4.359202] usbcore: registered new interface driver hub | ||
| + | [ 4.369958] usbcore: registered new device driver usb | ||
| + | [ 4.389472] SCSI subsystem initialized | ||
| + | [ 4.427621] kmodloader: done loading kernel modules from / | ||
| + | [ 4.453721] init: - preinit - | ||
| + | [ 5.273772] random: jshn: uninitialized urandom read (4 bytes read) | ||
| + | [ 5.360807] random: jshn: uninitialized urandom read (4 bytes read) | ||
| + | [ 5.474410] random: jshn: uninitialized urandom read (4 bytes read) | ||
| + | [ 6.144296] mtk_soc_eth 1e100000.ethernet swp0: PHY [mdio-bus: | ||
| + | [ 6.166211] mtk_soc_eth 1e100000.ethernet swp0: configuring for phy/rgmii link mode | ||
| + | Press the [f] key and hit [enter] to enter failsafe mode | ||
| + | Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level | ||
| + | [ 8.441218] UBIFS (ubi0:1): Mounting in unauthenticated mode | ||
| + | [ 8.452838] UBIFS (ubi0:1): background thread " | ||
| + | [ 8.485258] UBIFS (ubi0:1): recovery needed | ||
| + | [ 8.753298] random: crng init done | ||
| + | [ 8.760079] random: 7 urandom warning(s) missed due to ratelimiting | ||
| + | [ 9.206221] UBIFS (ubi0:1): recovery completed | ||
| + | [ 9.215286] UBIFS (ubi0:1): UBIFS: mounted UBI device 0, volume 1, name " | ||
| + | [ 9.230902] UBIFS (ubi0:1): LEB size: 65408 bytes (63 KiB), min./max. I/O unit sizes: 8 bytes/256 bytes | ||
| + | [ 9.249636] UBIFS (ubi0:1): FS size: 21846272 bytes (20 MiB, 334 LEBs), journal size 1111936 bytes (1 MiB, 17 LEBs) | ||
| + | [ 9.270493] UBIFS (ubi0:1): reserved for root: 1031852 bytes (1007 KiB) | ||
| + | [ 9.283722] UBIFS (ubi0:1): media format: w5/r0 (latest is w5/r0), UUID 907AC48D-B261-4D78-B446-E51308CA2E7C, | ||
| + | [ 9.471484] mount_root: overlay filesystem has not been fully initialized yet | ||
| + | [ 9.487468] mount_root: switching to ubifs overlay | ||
| + | [ 9.516608] urandom-seed: | ||
| + | [ 9.638014] procd: - early - | ||
| + | [ 9.644115] procd: - watchdog - | ||
| + | [ | ||
| + | [ | ||
| + | [ | ||
| + | Please press Enter to activate this console. | ||
| + | [ | ||
| + | [ | ||
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| + | [ | ||
| + | [ | ||
| + | [ | ||
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| + | [ | ||
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| + | [ | ||
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| + | [ | ||
| + | </ | ||
| </ | </ | ||
| Line 167: | Line 1526: | ||
| ===== Tags ===== | ===== Tags ===== | ||
| [[meta: | [[meta: | ||
| - | {{tag> | ||