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docs:hardware:start [2018/02/20 18:51] – ↷ Links adapted because of a move operation bobafetthotmaildocs:hardware:start [2018/03/14 04:49] – [Hardware] text -> link 1oh2
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   * Core System: [[docs:hardware:soc]] ([[docs:hardware:cpu]] , architecture specific)   * Core System: [[docs:hardware:soc]] ([[docs:hardware:cpu]] , architecture specific)
-  * Peripherals connected via: PCI, PCIe, [[docs:hardware:port.i2c|I2C]], SPI, [[docs:hardware:port.gpio|GPIO]], USB, Vendor specific+  * Peripherals connected via: [[wp>Conventional_PCI|PCI]][[wp>PCI_Express|PCIe]], [[docs:hardware:port.i2c|I2C]], [[wp>Serial_Peripheral_Interface_Bus|SPI]], [[docs:hardware:port.gpio|GPIO]], [[wp>USB]], Vendor specific
   * Special Hardware: [[docs:hardware:cryptographic.hardware.accelerators]]   * Special Hardware: [[docs:hardware:cryptographic.hardware.accelerators]]
   * Hardware developers often use interfaces that can directly write to chip registers or flash: [[docs:hardware:port.jtag|JTAG]], debug ports/pins   * Hardware developers often use interfaces that can directly write to chip registers or flash: [[docs:hardware:port.jtag|JTAG]], debug ports/pins
  • Last modified: 2020/08/19 01:15
  • by vitaliy86