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--- docs:techref:hardware:soc:soc.sifive [2018/11/02 18:05] – wigyori
+++ docs:techref:hardware:soc:soc.sifive [2023/05/28 14:23] (current) – update port status wigyori
@@ Line 1: / Line 1: @@
 ====== SiFive RISC-V SoCs ======
+RISC-V is a free, open, extensible instruction set architecture (ISA), the specification is now maintained by the nonprofit RISC-V Foundation.
-RISC-V is a free, open, extensible instruction set architecture (ISA), the specification is now maintained by the nonprofit RISC-V Foundation
+===== U540 =====
+U540 is the first available Linux-capable RISC-V SoC.
+   * 4+1 Multi-Core Coherent Configuration, up to 1.5 GHz
+   * 4x U54 RV64GC cores
+   * 1x E51 Management core
+   * 2MB L2 Cache
+   * DDR4 ECC memory
-==== U540 ====
+===== U740 =====
+U740 is the second generation of Linux-capable RISC-V SoC.
-U540 is the first (and currently only) available Linux-capable RISC-V SoC.
    * 4+1 Multi-Core Coherent Configuration, up to 1.5 GHz
-   * 4x U54 RV64GC Application Cores with Sv39 Virtual Memory Support
+   * 4x U74 RV64GC cores
-   * 1x E51 RV64IMAC Management Core
+   * 1x S7 Management core
-   * Coherent 2 MB L2 Cache
+   * 2MB L2 Cache
-   * 64-bit DDR4 with ECC
+   * DDR4 ECC memory
 ==== Status ====
+There are a couple options you can use to run RISC-V:
-There are three options you can use to run RISC-V:
+   * [[toh:hifive:unleashed|HiFive Unleashed]]
+   * [[toh:hifive:unmatched|HiFive Unmatched]]
-   * [[toh/hifive/unleashed|HiFive Unleashed]] (development board)
    * FPGA-based implementation (Virtex7)
-   * [[https://openwrt.org/docs/guide-user/virtualization/qemu#openwrt_in_qemu_risc-v|QEMU]] (cheapest option)
+   * [[docs:guide-user:virtualization:qemu#openwrt_in_qemu_risc-v|QEMU]] (cheapest option)
+   * Other SoCs (StarFive, Allwinner D1, work is in progress for these chips)
-Port status:
+Port status: sifiveu merged at 28/May/2023
-   * Builds with glibc
-   * Based on 4.19
-   * Until 4.19 is merged into trunk with some effort, build issues are expected with netfilter packages
-   * MUSL has linking issues
-   * Booting from SD
-   * 99% of the OpenWrt package repo built
-External package repository until the target is merged:
-<code>
-# cat /etc/opkg/customfeeds.conf
-src/gz riscv64_kmod http://openwrt.uid0.hu/riscv64/generic/generic-glibc/packages
-src/gz riscv64_base http://openwrt.uid0.hu/packages/riscv64_riscv64/base
-src/gz riscv64_packages http://openwrt.uid0.hu/packages/riscv64_riscv64/packages
-src/gz riscv64_luci http://openwrt.uid0.hu/packages/riscv64_riscv64/luci
-src/gz riscv64_telephony http://openwrt.uid0.hu/packages/riscv64_riscv64/telephony
-src/gz riscv64_routing http://openwrt.uid0.hu/packages/riscv64_riscv64/routing
-</code>
-To download from this repo, you'll need to remove this line from /etc/opkg.conf:
-<code>
-option check_signature 1
-</code>
-(Obviously, this have to be at your discretion.)
 ==== U540 Boot process ====
    * The SoC is initialized by a zero/first-stage bootloader called ZSBL/FSBL which is stored in ROM.
    * The FSBL goes on to boot BBL (Berkeley bootloader), which is a second-stage "proxy" kernel. A device-tree is passed on to the BBL.
    * The BBL image usually includes the kernel image, which is then booted.
-There were some controversies around the full openness of the ZSBL/FSBL (around the DDR init code), but that has been fixed/released in July. There are also efforts to replace the FSBL with a U-boot port, but that will still require the BBL to be built.
+There were some controversies around the full openness of the ZSBL/FSBL (around the DDR init code), but that has been fixed/released in July/18. There are also efforts to replace the FSBL with a U-boot port, but that will still require the BBL to be built.
+===== Devices =====
+The list of related devices:
+{{tagpage>riscv}},
+{{tagpage>riscv64}}
-===== Tags =====
-{{tag>riscv riscv64}}