SiFive RISC-V SoCs

RISC-V is a free, open, extensible instruction set architecture (ISA), the specification is now maintained by the nonprofit RISC-V Foundation

U540 is the first (and currently only) available Linux-capable RISC-V SoC.

• 4+1 Multi-Core Coherent Configuration, up to 1.5 GHz
• 4x U54 RV64GC Application Cores with Sv39 Virtual Memory Support
• 1x E51 RV64IMAC Management Core
• Coherent 2 MB L2 Cache
• 64-bit DDR4 with ECC

There are three options you can use to run RISC-V:

• HiFive Unleashed (development board)
• FPGA-based implementation (Virtex7)
• QEMU (cheapest option)

Port status:

• Builds with glibc
• Based on 4.19
• Until 4.19 is merged into trunk with some effort, build issues are expected with netfilter packages
• MUSL has linking issues
• Booting from SD
• Large number of packages built

External package repository until the target is merged:

src/gz riscv_base http://trabant.uid0.hu/openwrt/riscv64/packages/riscv64_riscv64/base
src/gz riscv_packages http://trabant.uid0.hu/openwrt/riscv64/packages/riscv64_riscv64/packages
src/gz riscv_luci http://trabant.uid0.hu/openwrt/riscv64/packages/riscv64_riscv64/luci

To download from this repo, you'll need to remove this line from /etc/opkg.conf:

option check_signature 1

• The SoC is initialized by a zero/first-stage bootloader called ZSBL/FSBL which is stored in ROM.
• The FSBL goes on to boot BBL (Berkeley bootloader), which is a second-stage “proxy” kernel. A device-tree is passed on to the BBL.
• The BBL image usually includes the kernel image, which is then booted.

There were some controversies around the full openness of the ZSBL/FSBL (around the DDR init code), but that has been released in July. There are also efforts to replace the FSBL with a U-boot port, but that will still require the BBL to be built.