SiFive RISC-V SOCs

RISC-V is a free, open, extensible instruction set architecture (ISA), the specification is now maintained by the nonprofit RISC-V Foundation

U540 is the first (and currently only) available Linux-capable RISC-V SoC.

• 4+1 Multi-Core Coherent Configuration, up to 1.5 GHz
• 4x U54 RV64GC Application Cores with Sv39 Virtual Memory Support
• 1x E51 RV64IMAC Management Core
• Coherent 2 MB L2 Cache
• 64-bit DDR4 with ECC

There are three options you can use to run RISC-V:

• HiFive Unleashed (development board)
• FPGA-based implementation (Virtex7)
• QEMU (cheapest option)

Port status:

• Builds with glibc
• Based on 4.19
• Until 4.19 is merged into trunk with some effort, build issues are expected with netfilter packages
• MUSL has linking issues
• Booting from SD
• Large number of packages built