SiFive RISC-V SoCs

RISC-V is a free, open, extensible instruction set architecture (ISA), the specification is now maintained by the nonprofit RISC-V Foundation

U540 is the first (and currently only) available Linux-capable RISC-V SoC.

• 4+1 Multi-Core Coherent Configuration, up to 1.5 GHz
• 4x U54 RV64GC Application Cores with Sv39 Virtual Memory Support
• 1x E51 RV64IMAC Management Core
• Coherent 2 MB L2 Cache
• 64-bit DDR4 with ECC

There are three options you can use to run RISC-V:

• HiFive Unleashed (development board)
• FPGA-based implementation (Virtex7)
• QEMU (cheapest option)

Port status:

• Builds with musl since 15/May/2019
• Based on 4.19
• Booting from SD
• 99% of the OpenWrt package repo built

External package repository until the target is merged:

# cat /etc/opkg/customfeeds.conf
src/gz riscv64_kmod http://openwrt.uid0.hu/riscv64/generic/generic/packages
src/gz riscv64_base http://openwrt.uid0.hu/packages/riscv64_riscv64/base
src/gz riscv64_packages http://openwrt.uid0.hu/packages/riscv64_riscv64/packages
src/gz riscv64_luci http://openwrt.uid0.hu/packages/riscv64_riscv64/luci
src/gz riscv64_telephony http://openwrt.uid0.hu/packages/riscv64_riscv64/telephony
src/gz riscv64_routing http://openwrt.uid0.hu/packages/riscv64_riscv64/routing

To download from this repo, you'll need to remove this line from /etc/opkg.conf:

option check_signature 1

(Obviously, this have to be at your discretion.)

• The SoC is initialized by a zero/first-stage bootloader called ZSBL/FSBL which is stored in ROM.
• The FSBL goes on to boot BBL (Berkeley bootloader), which is a second-stage “proxy” kernel. A device-tree is passed on to the BBL.
• The BBL image usually includes the kernel image, which is then booted.

There were some controversies around the full openness of the ZSBL/FSBL (around the DDR init code), but that has been fixed/released in July/18. There are also efforts to replace the FSBL with a U-boot port, but that will still require the BBL to be built.

The list of related devices: riscv, riscv64