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| docs:techref:hardware:soc:soc.mediatek [2021/02/01 16:53] – [Ralink ramips] danitool | docs:techref:hardware:soc:soc.mediatek [2023/12/24 03:24] (current) – [Ralink ramips] mt7620 and mt7628 driver lmita | ||
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| Line 28: | Line 28: | ||
| | ::: | MT7620 | | ::: | MT7620 | ||
| | ::: | ::: | MT7620n | SDR/DDR1/2 | 2T2R | 24KEc | [[toh: | | ::: | ::: | MT7620n | SDR/DDR1/2 | 2T2R | 24KEc | [[toh: | ||
| - | | ::: | MT7621 | + | | ::: | MT7621 |
| + | | ::: | ::: | MT7621ST | DDR2/3 | n/a | 1004Kc | [[toh: | ||
| | ::: | [[https:// | | ::: | [[https:// | ||
| | ::: | MT7688 | | ::: | MT7688 | ||
| Line 40: | Line 41: | ||
| * RT5350 is still available and cheaper, [[http:// | * RT5350 is still available and cheaper, [[http:// | ||
| * see here for a comparison: [[http:// | * see here for a comparison: [[http:// | ||
| + | * These use the '' | ||
| * MT7621 | * MT7621 | ||
| * 2 cores, 4 threads: | * 2 cores, 4 threads: | ||
| * MT7621AT | * MT7621AT | ||
| + | * MT7621DAT: 128MB integrated RAM | ||
| * 1 core, 2 threads: | * 1 core, 2 threads: | ||
| * MT7621ST, MT7621NT | * MT7621ST, MT7621NT | ||
| Line 52: | Line 55: | ||
| * MT7628K: Embedded 8MB DRAM and L-shape | * MT7628K: Embedded 8MB DRAM and L-shape | ||
| * MT7628N: Same as MT7628A, but without PCle and IoT modes | * MT7628N: Same as MT7628A, but without PCle and IoT modes | ||
| + | * MT7628DAN: 64MB integrated RAM | ||
| + | * The chip uses a driver from the '' | ||
| + | ===== RGMII configuration ===== | ||
| + | On MT7620A and likely other Ralink / Mediatek SOCs, the RGMII delay is set with the Port I control register in the GSW (gigabit switch) subsystem | ||
| + | |||
| + | for boards with uboot and an available console (option 4?), the register can be read with the command | ||
| + | |||
| + | md 0x10117014 1 | ||
| + | |||
| + | and the following bits tell you the OEM bootloader / chip defaults | ||
| + | |||
| + | |BIT(2)|RX no delay| | ||
| + | |BIT(3)|TX delay| | ||
| + | |BITS(16, 20)|PHY_BASE| | ||
| + | |BITS(24, 28)|PHY_DISABLE| | ||
| + | |||
| + | For a complete explanation, | ||
| + | |||
| + | example: | ||
| + | |||
| + | 10117014: 1f08000c | ||
| + | |||
| + | c --> 1100 --> TX delay only | ||
| + | |||
| + | 8 --> PHY_BASE address | ||
| + | |||
| + | 1f --> internal PHYs disabled | ||
| + | |||
| + | |||
| + | ---- | ||
| + | Remember: You have to read bits from right to left. | ||
| + | For example '' | ||
| + | < | ||
| + | 0001 1111 0000 1000 0000 0000 0000 1100 | ||
| + | | ||
| + | 28 | ||
| + | </ | ||
| ===== MediaTek xDSL ===== | ===== MediaTek xDSL ===== | ||
| Line 70: | Line 110: | ||
| * [[http:// | * [[http:// | ||
| * combine with RT63095 AFE (Analog Front-End) for VDSL2 | * combine with RT63095 AFE (Analog Front-End) for VDSL2 | ||
| + | |||
| + | |||
| ==== Linux support for MediaTek xDSL ==== | ==== Linux support for MediaTek xDSL ==== | ||