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| docs:techref:hardware:soc:soc.broadcom.bcm63xx:smp [2018/06/07 17:43] – link fixed tmomas | docs:techref:hardware:soc:soc.broadcom.bcm63xx:smp [2019/09/09 17:40] (current) – wip infobox vgaetera | ||
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| ====== SMP/CMT Broadcom 63xx ====== | ====== SMP/CMT Broadcom 63xx ====== | ||
| + | {{page> | ||
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| An example of SMP initialization on BCM6358 SoC: [[http:// | An example of SMP initialization on BCM6358 SoC: [[http:// | ||
| < | < | ||
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| So no benefit using a different core for the main thread. | So no benefit using a different core for the main thread. | ||
| - | |||
| ===== CP0 Registers ===== | ===== CP0 Registers ===== | ||
| - | |||
| ==== Configuration Registers ==== | ==== Configuration Registers ==== | ||
| To know if your CPU has concurrent multi-threading support (CMT) check **bit 18** at BRCM Configuration register (read_c0_brcm_config_0): | To know if your CPU has concurrent multi-threading support (CMT) check **bit 18** at BRCM Configuration register (read_c0_brcm_config_0): | ||
| 0 = 1 core\\ | 0 = 1 core\\ | ||
| 1 = 2 cores, multi-thread supported\\ | 1 = 2 cores, multi-thread supported\\ | ||
| - | |||
| Also check the **bit 12**:\\ | Also check the **bit 12**:\\ | ||
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| * Fatal bug causing jffs2 data corruption -> temporal workaround [[https:// | * Fatal bug causing jffs2 data corruption -> temporal workaround [[https:// | ||
| - | {{tag>wip bcm63xx}} | + | ===== Devices ===== |
| + | The list of related devices: | ||
| + | {{tagpage> | ||