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--- docs:techref:hardware:soc:soc.broadcom.bcm63xx:smp [2018/03/31 23:22] – ↷ Page moved from docs:hardware:soc:soc.broadcom.bcm63xx:smp to docs:techref:hardware:soc:soc.broadcom.bcm63xx:smp bobafetthotmail
+++ docs:techref:hardware:soc:soc.broadcom.bcm63xx:smp [2019/09/09 17:40] (current) – wip infobox vgaetera
@@ Line 1: / Line 1: @@
 ====== SMP/CMT Broadcom 63xx ======
-An example of SMP initialization on BCM6358 SoC: http://pastebin.com/wV3njK7c taken from
+{{page>meta:infobox:wip&noheader&nofooter&noeditbtn}}
+An example of SMP initialization on BCM6358 SoC: [[http://pastebin.com/wV3njK7c]] taken from
 <del>[[http://www.livebox-floss.com/Products//LiveBox/LiveBox1/Thomson/vunknown/linux-2.6.12.tar.bz2|linux-2.6.12.tar.bz2]]</del>, mirror ->[[https://drive.google.com/uc?export=download&id=0B-EMoBe-_OdBRnppenZMOExOUEU|linux-2.6.12-inv.zip]]
@@ Line 60: / Line 62: @@
 Then the main thread will be the core1. This is important since the BCM6358 SoC cores haven't the same features:
-^ BCM6358 ^  Data cache  ^  Instruction cache  ^
+^ BCM6358   ^  Data cache  ^  Instruction cache  ^
-|  core0  |  16kB  |  32kB  |
+|   core0   |     16kB     |        32kB         |
-|  core1  | ::: |  16kB  |
+|   core1   | :::          |        16kB         |
-This parameter is located between **offsets 0x014-0x017** in [[docs:techref:bootloader:cfe#bcm63xx.cfe|CFE]]. We can change it HEX editing the CFE. Setting the value to 0, makes the core0 the main thread. This brings 32kB instead 16kB icache to the operating system and therefore increases the performance.
+This parameter is located between **offsets 0x014-0x017** in [[docs:techref:bootloader:cfe#bcm63xx_cfe|CFE]]. We can change it HEX editing the CFE. Setting the value to 0, makes the core0 the main thread. This brings 32kB instead 16kB icache to the operating system and therefore increases the performance.
 Some CFEs allow to change the Main thread using the command line interface. This option is probably only present in most recent SoCs such as BCM6368.
 BCM6368 SoC cores are identical:
-^ BCM6368 ^  Data cache  ^  Instruction cache  ^
+^ BCM6368   ^  Data cache  ^  Instruction cache  ^
-|  core0  |  32kB  |  64kB  |
+|   core0   |     32kB     |        64kB         |
-|  core1  | ::: |  64kB  |
+|   core1   | :::          |        64kB         |
 So no benefit using a different core for the main thread.
 ===== CP0 Registers =====
 ==== Configuration Registers ====
 To know if your CPU has concurrent multi-threading support (CMT) check **bit 18** at BRCM Configuration register (read_c0_brcm_config_0):\\
 = 1 core\\
 = 2 cores, multi-thread supported\\
 Also check the **bit 12**:\\
@@ Line 251: / Line 250: @@
 </code>
- -> http://pastebin.com/JWCFs0qz
+ -> [[http://pastebin.com/JWCFs0qz]]
 Note:
@@ Line 261: / Line 260: @@
 ===== OpenWrt status =====
   * No support in BCM6358, mainly caused by the shared TLB.
-  * BCM6362 and BCM6368 are supported. Available through the SMP subtarget in trunk versions:\\ https://dev.openwrt.org/changeset/36526\\ https://dev.openwrt.org/changeset/36527
+  * BCM6362 and BCM6368 are supported. Available through the SMP subtarget in trunk versions:\\ [[https://dev.openwrt.org/changeset/36526]]\\ [[https://dev.openwrt.org/changeset/36527]]
-  * Fatal bug causing jffs2 data corruption -> temporal workaround https://dev.openwrt.org/changeset/40396
+  * Fatal bug causing jffs2 data corruption -> temporal workaround [[https://dev.openwrt.org/changeset/40396]]
+===== Devices =====
+The list of related devices:
+{{tagpage>bcm63xx}}
-{{tag>wip bcm63xx}}