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docs:techref:hardware:soc:soc.allwinner.starfive [2024/03/02 11:32] – created wigyoridocs:techref:hardware:soc:soc.allwinner.starfive [2024/03/02 17:23] (current) – cosmetic wigyori
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 RISC-V is a free, open, extensible instruction set architecture (ISA), the specification is now maintained by the nonprofit RISC-V Foundation. RISC-V is a free, open, extensible instruction set architecture (ISA), the specification is now maintained by the nonprofit RISC-V Foundation.
  
-StarFive produces a number of RISC-V SoCs, mostly based on the SiFive designs.+StarFive produces a number of RISC-V SoCs, mostly based on the SiFive designs. Upstreaming the device / interface support for them is in progress.
  
 ==== Status ==== ==== Status ====
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    * Official doc site: https://doc-en.rvspace.org/index.html    * Official doc site: https://doc-en.rvspace.org/index.html
  
-===== StarFive SoCs =====+===== Supported StarFive SoCs =====
  
 ^ Target ^ CPU      ^ Series      ^ CPU cores ^ CPU MHz ^  Notes ^ ^ Target ^ CPU      ^ Series      ^ CPU cores ^ CPU MHz ^  Notes ^
-^ starfive | JH7100 | U74 |  2  |  1.0GHz |   | +^ starfive | JH7100 | U74 |  2  |  1.0GHz | RV64GC  | 
-^ starfive | JH7110 | U74 |  4  |  1.5GHz |   |+^ starfive | JH7110 | U74 |  4  |  1.5GHz | RV64GC  |
  
 ==== JH7100 boards ==== ==== JH7100 boards ====
  • Last modified: 2024/03/02 11:32
  • by wigyori